TSX5070FN STMicroelectronics, TSX5070FN Datasheet - Page 9

• Manufacturer Part Number: TSX5070FN
• Manufacturer: STMicroelectronics
• Type: PCMr

Specifications of TSX5070FN

• Number Of Channels: 1
• Gain Control: Programmable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Package Type: PLCC
• Operating Supply Voltage (typ): ±5V
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): ±5.25V
• Operating Supply Voltage (min): ±4.75V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

CONTROL REGISTER INSTRUCTION
The first byte of a READ or WRITE instruction to
the Control Register is as shown in table 1. The
second byte functions are detailed in table 2.
MASTER CLOCK FREQUENCY SELECTION
A Master clock must be provided to COMBO IIG
for operation of the filter and coding/decoding
functions. The MCLK frequency must be either
512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or
4.096 MHz and must be synchronous with BCLK.
Bits F1 and F0 (see table 2) must be set during
initialization to select the correct internal divider.
CODING LAW SELECTION
Bits "MA" and "IA" in table 2 permit the selection
of
even-bit inversion.
Table 2: Control Register Byte 2 Functions
Table 3: Coding Law Conventions.
Note: The MSB is always the first PCM bit shifted in or out of COMBO IIG.
(*) State at power-on initialization (bit 4 = 0)
V
V
V
IN
IN
IN
F1
7
0
0
1
1
255 coding or A-law coding with or without
= +Full Scale 1
= 0V
= -Full Scale
F0
6
0
1
0
1
1
0
0
MA
5
0
1
1
0
1
1
0
0
1
1
0
Bit Number
m255 Law
MSB LSB
IA
X
4
0
1
0
1
1
0
0
1
1
0
DN
3
0
1
0
1
1
0
0
1
1
0
DL
2
0
1
0
0
1
1
0
1
1
0
0
AL
0
1
1
0
X
1
0
1
even bit inversion
True A-law with
ANALOG LOOPBACK
Analog Loopback mode is entered by setting the
"AL" and "DL" bits in the Control Register as shown
in table 2. In the analog loopback mode, the Trans-
mit input VF
ternally connected to the VF
loop from the Receive PCM Register back to the
Transmit PCM Register. The VF
tive, and the programmed settings of the Transmit
and Receive gains remain unchanged, thus care
must be taken to ensure that overload levels are
not exceeded anywhere in the loop.
Hybrid balancing must be disabled for meaning
ful analog loopback Function.
DIGITAL LOOPBACK
Digital Loopback mode is entered by setting the
"DL" bit in the Control Register as shown in table 2.
1
0
0
1
MSB LSB
0
1
1
0
PP
0
0
1
1
0
0
1
MCLK = 512 kHz
MCLK = 1. 536 or 1. 544 MHz
MCLK = 2. 048 MHz
MCLK = 4. 096 MHz
Select . 255 Law
A–law, Including Even Bit Inversion
A–Law, No Even Bit Inversion
Delayed Data Timing
Non–delayed Data Timing
Normal Operation
Digital Loopback
Analog Loopback
Power Amp Enabled in PDN
Power Amp Disabled in PDN
0
1
1
0
X
I is isolated from the input pin and in-
1
0
0
1
0
1
1
0
1
1
0
0
Function
1
0
0
1
*
*
even bit inversion
R
A-law without
*
1
0
0
1
TS5070 - TS5071
O output, forming a
MSB LSB
R
O pin remains ac-
1
0
0
1
*
*
1
0
0
1
1
0
0
1
1
0
0
1
9/32
1
0
0
1