TSX5070FN STMicroelectronics, TSX5070FN Datasheet - Page 6

• Manufacturer Part Number: TSX5070FN
• Manufacturer: STMicroelectronics
• Type: PCMr

Specifications of TSX5070FN

• Number Of Channels: 1
• Gain Control: Programmable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Package Type: PLCC
• Operating Supply Voltage (typ): ±5V
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): ±5.25V
• Operating Supply Voltage (min): ±4.75V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

INTERFACE, CONTROL, RESET
TS5070 - TS5071
FUNCTIONAL DESCRIPTION
POWER-ON INITIALIZATION
When power is first applied, power-on reset cir-
cuitry initializes COMBO IIG and puts it into the
power-down state. The gain control registers for
the transmit and receive gain sections are pro-
grammed for no output, the hybrid balance circuit
is turned off, the power amp is disabled and the
device is in the non-delayed timing mode. The
Latch Direction Register (LDR) is pre-set with all
IL pins programmed as inputs, placing the SLIC
interface pins in a high impedance state. The
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Name
CCLK
CI/O
MR
CO
IL5
IL4
IL3
IL2
IL1
IL0
CS
CI
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
TS5070
FN
23
24
25
26
13
12
11
14
15
6
7
–
TS5071
16
17
18
10
11
N
–
4
5
9
8
–
–
Interface
Latches
Control Clock
Control Data
Input/output
Control Data
Input
Control Data
Output
Chip Select
Master Reset
Function
IL5 through IL0 are available on the TS5070,
IL4 through IL0 are available on the TS5071.
Each interface Latch I/O pin may be individually
programmed as an input or an output determined by the
state of the corresponding bit in the Latch Direction
Register (LDR) . For pins configured as inputs, the logic
state sensed on each input is latched into the interface
Latch Register (ILR) whenever control data is written to
COMBO IIG, while CS is low, and the information is
shifted out on the CO (or CI/O) pin. When configured as
outputs, control data written into the ILR appears at the
corresponding IL pins.
This clock shifts serial control information into or out of CI
or CO (or CI/O) when the CS input is low depending on
the current instruction. CCLK may be asynchronous with
the other system clocks.
This is Control Data I/O pin wich is provided on the
TS5071. Serial control information is shifted into or out of
COMBO IIG on this pin when CS is low. The direction of
the data is determined by the current instruction as defined
in Table 1.
These are separate controls, availables only on the
TS5070. They can be wired together if required.
When this pins is low, control information can be written to
or read from the COMBO IIG via the CI and CO pins (or
CI/O).
This logic input must be pulled low for normal operation of
COMBO IIG. When pulled momentarily high, all
programmable registers in the device are reset to the
states specified under "Power–on Initialization".
CI/O pin is set as an input ready for the first con-
trol byte of the initialization sequence. Other initial
states in the Control Register are indicated in Ta-
ble 2.
A reset to these same initial conditions may also be
forced by driving the MR pin momentarily high. This
may be done either when powered-up or down. For
normal operation this pin must be pulled low. If not
used, MR should be hard-wired to ground.
The desired modes for all programmable functions
may be initialized via the control port prior to a
Power-up command.
Description