TSX5070FN STMicroelectronics, TSX5070FN Datasheet - Page 8

• Manufacturer Part Number: TSX5070FN
• Manufacturer: STMicroelectronics
• Type: PCMr

Specifications of TSX5070FN

• Number Of Channels: 1
• Gain Control: Programmable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Package Type: PLCC
• Operating Supply Voltage (typ): ±5V
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): ±5.25V
• Operating Supply Voltage (min): ±4.75V
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TS5070 - TS5071
struction; and bit 0 is not used. To shift control data
into COMBO IIG, CCLK must be pulsed high 8
times while CS is low. Data on the CI or CI/O input
is shifted into the serial input register on the falling
edge of each CCLK pulse. After all data is shifted
in, the contents of the input shift register are de-
coded, and may indicate that a 2nd byte of control
data will follow. This second byte may either be de-
fined by a second byte-wide CS pulse or may follow
the first continuously, i.e. it is not mandatory for CS
to return high in between the first and second con-
trol bytes. On the falling edge of the 8
pulse in the 2nd control byte the data is loaded into
the appropriate programmable register. CS may re-
main low continuously when programming succes-
Table 1: Programmable Register Instructions
PROGRAMMABLE FUNCTIONS
POWER-UP/DOWN CONTROL
Following power-on initialization, power-up and
power-down control may be accomplished by
writing any of the control instructions listed in ta-
ble 1 into COMBO IIG with the "P" bit set to "0"
for power-up or "1" for power-down. Normally it is
recommended that all programmable functions be
initially programmed while the device is powered
down. Power state control can then be included
with the last programming instruction or the sepa-
8/32
Notes: 1. Bit 7 of bytes 1 and 2 is always the first bit clocked into or out of the CI, CO or CI/CO pin.
Single Byte Power–up/down
Write Control Register
Read–back Control Register
Write Latch Direction Register (LDR)
Read Latch Direction Register
Write Latch Content Register (ILR)
Read Latch Content Register
Write Transmit Time–slot/port
Read–back Transmit Time–slot/port
Write Receive Time–slot/port
Read–back Receive Time–slot/port
Write Transmit Gain Register
Read Transmit Gain Register
Write Receive Gain Register
Read Receive Gain Register
Write Hybrid Balance Register
Read Hybrid Balance Register
Write Hybrid Balance Register
Read Hybrid Balance Register
Write Hybrid Balance Register
Read Hybrid Balance Register
2. "P" is the power-up/down control bit, see "Power-up" section ("0" = Power Up "1" = Power Down).
Function
1
2
3
1
2
3
th
P
7
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
CCLK clock
X
6
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
X
0
0
5
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
Byte 1
X
4
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
X
3
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
sive registers, if desired. However CS should be set
high when no data transfers are in progress.
To readback interface Latch data or status informa-
tion from COMBO IIG, the first byte of the appropri-
ate instruction is strobed in during the first CS pulse,
as defined in table 1. CS must then be taken low for
a further 8 CCLK cycles, during which the data is
shifted onto the CO or CI/O pin on the rising edges
of CCLK. When CS is high the CO or CI/O pin is in
the high-impedance TRI-STATE, enabling the CI/O
pins of many devices to be multiplexed together.
Thus, to summarize, 2-byte READ and WRITE in-
structions may use either two 8-bit wide CS pulses
or a single 16-bit wide CS pulse.
rate single-byte instruction. Any of the program-
mable registers may also be modified while the
device is powered-up or down be setting the "P"
bit as indicated. When the power up or down con-
trol is entered as a single byte instruction, bit one
(1) must be set to a 0.
When a power-up command is given, all de-acti-
vated circuits are activated, but the TRI-STATE
PCM output(s), D
high impedance state until the second FS
after power-up.
X
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
0 (and D
See Table 10
See Table 10
See Table 2
See Table 2
See Table 4
See Table 4
See Table 5
See Table 5
See Table 6
See Table 6
See Table 6
See Table 6
See Table 7
See Table 7
See Table 8
See Table 8
See Table 9
See Table 9
X
Byte 2
1), will remain in the
None
X
pulse