N681622YG Nuvoton Technology Corporation of America, N681622YG Datasheet
N681622YG
Specifications of N681622YG
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N681622YG Summary of contents
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... Tone Range ( N681386DG - N681387DG N681386YG - N681387YG N681622YG - WARNING ! HIGH VOLTAGE WARNING USE EXTREME CAUTION High voltage sources could cause serious injury or death if not used in accordance with design and/or user specifications, if they are used by untrained or unqualified personnel. Before testing Nuvoton’s products read and understand all instructions, and safety procedures as in industry standard safe practices ...
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PIN CONFIGURATION Figure 1: N681386/87 Pin Configuration Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 2 of 164 N681386/87 January 2010 ...
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Figure 2: N681622 Subscriber Line Feed Circuit (SLFC) Pin Configuration Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 3 of 164 N681386/87 January 2010 ...
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PIN DESCRIPTION 4.1. N681386/87 Pin Description Pin Name Pin No. VDD1 1 Line-driver 3.3 V supply RIP 2 Positive RING Driver current source & Voltage sense RIN 3 Negative RING Driver current source TVB 4 Positive TIP Driver Base ...
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Pin Name Pin No. DCH 28 DC/DC Converter Current Sense Higher input Voltage DCL 29 DC/DC Converter Current Sense Lower input Voltage VDD2 30 3.3 V Analog AC path and reference Supply Voltage GND2 31 Analog AC path and reference ...
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N681622 Pin Description Pin Name Pin No. RIP 1 Ring Driver Pull up Current from 34.8 Ohm resistor TVB 2 Tip Pull-Up Driver control voltage TPP 3 Tip Driver Pull up Current from 34.8 Ohm resistor RVB 4 Ring ...
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BLOCK DIAGRAM Figure 3: N681386/87 Block Diagram Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 7 of 164 N681386/87 January 2010 ...
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TABLE OF CONTENTS 1. DESCRIPTION ........................................................................................................................................... 1 2. FEATURES ................................................................................................................................................ 1 3. PIN CONFIGURATION .............................................................................................................................. 2 4. PIN DESCRIPTION .................................................................................................................................... 4 4.1. N681386/87 PIN DESCRIPTION ............................................................................................................... 4 4.2. N681622 PIN DESCRIPTION .................................................................................................................... 6 ...
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AUTOMATIC TRANSITIONS ................................................................................................................... 29 12.1.1.3.1. POWER ALARM AUTOMATIC REACT ................................................................................................... 29 12.1.1.3.2. SETTING RING AUTOMATIC .................................................................................................................. 29 12.1.1.3.3. SETTING LOOP CLOSURE DETECT AUTOMATIC REACT .................................................................. 30 12.1.1.4. POLARITY REVERSAL ............................................................................................................................ 32 12.1.1.4.1. HARD ...
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DC/DC CONVERSION (INDUCTOR) ....................................................................................................... 60 12.1.8.2. EXTERNAL BATTERY SWITCHING ........................................................................................................ 62 12.2. DIGITAL INTERFACE .............................................................................................................................. 63 12.2.1. CLOCK GENERATION ............................................................................................................................ 63 12.2.2. PCM INTERFACE .................................................................................................................................... 64 12.2.2.1. WIDEBAND AND NARROWBAND OPERATION .................................................................................... 65 ...
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DIAGNOSTIC CONTROL 1 ...................................................................................................................... 89 14.3.3. DIAGNOSTIC CONTROL AND 5 ................................................................................................. 90 14.3.4. DIAGNOSTIC CONTROL 6 AND 7 (READ ONLY) .................................................................................. 91 14.3.5. DIAGNOSTIC CONTROL 8 (READ ONLY) .............................................................................................. 92 14.3.6. ...
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LOOP CLOSURE DEBOUNCE .............................................................................................................. 110 14.7.9. RING TRIP DEBOUNCE INTERVAL ...................................................................................................... 110 14.7.10. PWM PERIOD ........................................................................................................................................ 110 14.7.11. DC/DC CONTROLLER CONTROL ........................................................................................................ 111 14.7.12. ON-HOOK VOLTAGE ............................................................................................................................ 111 14.7.13. GROUND MARGIN VOLTAGE .............................................................................................................. ...
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POLARITY .............................................................................................................................................. 125 14.12.5. COMMON MODE VOLTAGE ................................................................................................................. 126 14.12.6. TIP EMITTER VOLTAGE FOR TRANSISTORS QT1 SENSE (READ ONLY) ....................................... 126 14.12.7. TIP VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY) .......................................................... 126 14.12.8. RING ...
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IMPEDANCE MATCHING COEFFICIENT RAM CONTROL .................................................................. 139 14.19.6.4. PCM SCALING ....................................................................................................................................... 140 14.19.6.5. RESERVED REGISTERS ...................................................................................................................... 140 14.19.6.6. FILTER BYPASS .................................................................................................................................... 140 15. TIMING DIAGRAM ................................................................................................................................. 141 15.1. PCM TIMING DIAGRAM FOR NON-GCI ...
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LIST OF FIGURES Figure 1: N681386/87 Pin Configuration ........................................................................................................................ 2 Figure 2: N681622 Subscriber Line Feed Circuit (SLFC) Pin Configuration .................................................................. 3 Figure 3: N681386/87 Block Diagram ............................................................................................................................ 7 Figure 4: AC signal Path .............................................................................................................................................. 25 Figure 5: DC ...
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Figure 38: GCI PCM Timing ....................................................................................................................................... 142 Figure 39: SPI Timing (Non-Daisy Chain Mode) ........................................................................................................ 144 Figure 40: In-band Transmit Frequency Response .................................................................................................... 145 Figure 41: In-band Receive Frequency Response ..................................................................................................... 145 Figure 42: Transmit Group Delay Distortion ............................................................................................................... 146 ...
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LIST OF TABLES Table 1: N681386/87 Pin Description ............................................................................................................................. 5 Table 2: N681622 Pin Description .................................................................................................................................. 6 Table 3: Programmable Ranges for DC Line Feed ...................................................................................................... 26 Table 4: Linefeed States .............................................................................................................................................. 28 Table 5: Operation Modes ............................................................................................................................................ 29 ...
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ABSOLUTE MAXIMUM RATINGS 9.1. Single Programmable Extended Codec/SLCC (N681386/87) Condition Junction temperature Storage temperature range LQFP-48 Thermal Resistance, typical QFN-48 Thermal Resistance, typical Voltage applied to any pin Input current applied to any digital input pin ESD (Human Body ...
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OPERATING CONDITIONS 10.1. Single Programmable Extended Codec/SLCC (N681386/87) Condition Industrial operating temperature Supply voltage ( Ground voltage ( Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and ...
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ELECTRICAL CHARACTERISTICS 11.1. GENERAL PARAMETERS (N681386/87 = Symbol Parameters V Logic Input LOW Voltage IL V Logic Input HIGH Voltage IH V Threshold point ...
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Symbol Parameters Current Forward/Reverse Active I 1. Typical values 25°C , VDD = 3 All min/max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all specifications are 100 percent tested. 3. The supply ...
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MONITORING A/D PARAMETERS V =3. 3. Symbol INL Integral Nonlinearity (8-bit resolution) DNL Differential Nonlinearity (8-bit resolution) Gain Error (Current) Gain Error (Voltage) Sample Rate per channel Number of channels ...
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TO 4-WIRE CONVERSION PARAMETERS 0 V = PARAMETER SYM. Return Loss R L Trans hybrid Balance H B 11.7. 2-WIRE PARAMETERS 0 V ...
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ANALOG DISTORTION AND NOISE PARAMETERS V =3.13 V – PARAMETER SYM. Total Distortion vs. Level D 1020 Hz, C-Message Weighted LTu Tone u-Law Total Distortion vs. Level 1020 Hz, ...
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FUNCTIONAL DESCRIPTION Interface Interface Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC PCM PCM PCM PCM Figure 4: AC signal Path Page 25 of 164 N681386/87 January 2010 ...
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BORSCHT FUNCTIONALITY The N681386/87 connects to the TIP and RING (POTS - Plain Old Telephone Service) interface and performs the so- called BORSCHT and AC transmission functions. Following are the BORSCHT functions: Battery Feed Over-Voltage Protection Ringing (Balanced / ...
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The control circuit for TIP or RING is illustrated in Figure 5 and utilizes a three transistor discrete Linefeed circuit. Transistors Q1 and Q2 drive the voltages on the subscriber loop while transistor Q3 provides additional isolation. The Line Driver ...
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LINEFEED STATES OF OPERATION The N681386/87 can operate in eleven states, as shown below. State Open Forward Active Forward ON-HOOK Transmission TIP Open Ringing Reverse Active Reverse ON-HOOK Transmission RING Open Forward Idle Reverse Idle Calibration 12.1.1.1.1. OPEN STATE ...
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RING OPEN STATE All control currents to the external circuitry associated with RING are shut off and keeps TIP active. 12.1.1.1.5. RINGING STATE Drives the ringing waveforms onto the loop 12.1.1.1.6. CALIBRATION STATE Calibration state is used to compensate ...
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SETTING LOOP CLOSURE DETECT AUTOMATIC REACT Setting LAMC:LCDA[0] address (0x43) bit makes the channel automatically enter the Active state from the ON-HOOK Transmission, Idle, TIP Open, and RING Open states upon Loop Closure Detect. Furthermore, the channel will transition ...
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The device continuously monitors voltages on the line driver, driving them to target voltages appropriate to the actual linefeed state as summarized below. Linefeed State Open Forward Active Forward ON-HOOK Transmission TIP Open Ringing Reverse Active Reverse ON-HOOK Transmission RING ...
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POLARITY REVERSAL The Linefeed states which have Forward or Reverse incarnation (Active, Idle and ON-HOOK Transmission states) can have the polarity reversed two different ways. In addition, the line (TIP or RING) which is at VOH can be collapsed ...
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The ramp rate for steps 2 and 4 above is determined by the Ramp Rate bit APG:RAMP[7]. 12.1.1.5. WINK FUNCTION POLARITY REVERSAL A Wink function is used for the ‘message waiting’ lamp in telephone sets. For this function to take ...
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Register Bit(s) Address APG PALT[7:0] 0x9F Table 11: PWM DC/DC Power Alarm Counter 12.1.2.1. THERMAL OVERLOAD In addition to voltage and current monitoring described in section 6.1.1.1 “Linefeed States of Operation”, N681386/87 continuously monitors the power dissipation of each external ...
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TEMPERATURE MONITOR The device contains an on-chip temperature sensor that senses the temperature inside the package. The sensor is read through TEMP:TS[7:0] register (0x99) which is READ ONLY register. The temperature T in °C is given by the following ...
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TONE GENERATION There are two tone generators Oscillator1 (OS1), and Oscillator2 (OS2). These can be used to generate signals such as dial tone, busy tone, and various test tones which can be sent either on the transmit or receive ...
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The initial condition for Oscillator m, OSmICL[15:0], can be calculated using the following equation. The following equations can be used for both Narrowband and Wideband. = OmIC [ “A” is calculated as the ratio of desired ...
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OS1AT OS1AT INT Logic INT Logic IE2:O1AE IE2:O1AE INT2:O1I INT2:O1I INT2:O1A INT2:O1A IE2:O1E IE2:O1E OS1C OS1C Each tone generator contains two timers, one for setting the active period and the other for the inactive period. Each period can be programmed ...
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Figure 9: Zero Crossing for Tone Generation Oscillator 2 is also specifically used to generate the Ringing signal and is unavailable for other functions during ringing. FSK generation does not utilize either one of the tone generation oscillators. ...
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RING signal will end without a DC component recommended that settings be reprogrammed only when the oscillator is disabled. Register Name Register Name RMPC TRAP[7] OS2CL O2C[17:0] OS2CH OS2ICL O2IC[15:0] OS2ICH OS2RPD OS2RPD[7:0] OSN O2E[1] OS2ATL O2ON[15:0] ...
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SINUSOIDAL RINGING Sinusoidal Ringing is selected by setting RMPC:TRAP[7] address (0xC1) to LOW. For a desired frequency f calculated and programmed as before (see section Tone Generation). The oscillator initial condition for oscillator 2 is set in register O2IC[15:0] ...
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TRAPEZOIDAL RINGING Trapezoidal Ringing is selected by writing RMPC:TRAP[ address (0xC1). Three parameters are required to specify a Trapezoidal RING Signal and they as follows: • Desired frequency f (period T) t • Desired amplitude A PK ...
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RINGING DC OFFSET AND COMMON MODE BIAS A Ringing DC offset voltage V can be defined by setting ROFFS:ROS[5:0] ROFF Ringing DC Offset is enabled when ROFFS:ROS[5:0] contains a non-zero value. V from, the AC ringing signal depending on ...
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LINEFEED CONSIDERATIONS DURING RINGING To maintain proper biasing of the external bipolar transistors the generated Ringing signal should stay between the Ringing voltage rails (GNDA and the ringing signal approaches the rails the signal will distort. ...
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RING TRIP DETECTION The Ring Trip Detection mechanism is used to recognize an off-hook event during Ringing. The N681386/87 monitors the Loop current through the Loop current circuitry (available at LPI:ILP[11:0] address (0x90)). If the shadow Linefeed state LS:SLS[7:4] ...
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In general, only one detection path should be utilized at one time by maximizing the Ring Trip Threshold value of the unwanted path. Register Bit(s) Address RTTA ARTT[5:0] 0x55 RTTD DRTT[5:0] 0x67 RTDBA ARTDI[7:0] 0x48 RTDBD DRTDI[7:0] 0x68 0x51 RTDFCLD ...
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SUPERVISION (SIGNALING) 12.1.4.1. LOOP CLOSURE DETECTION The recognition of an off-hook event outside Ringing is controlled by the Loop Closure Detect mechanism. Figure 16 shows the functional block. Figure 15: Loop Closure Detector Block Diagram Loop current monitoring circuitry ...
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Register Bit(s) Address LCT LCT[5:0] 0x53 Loop Closure Threshold LPI ILP[11:0] 0x90 Loop Closure LCTHY LCHYEN[6] 0x54 Enable Hysteresis Loop Closure Threshold Off-Hook to LCTHY LCTOFF[5:0] 0x54 ON-HOOK state Enable Hysteresis Loop Closure Detect Debounce LCDB LCDI[7:0] 0x47 Interval LCDCL ...
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GROUND KEY DETECTION Ground Key Detect (GKD) senses a DC current imbalance between the TIP and RING terminals when the RING terminal is connected to ground. This feature is commonly associated with PBX signaling. The feature is enabled in ...
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The resulting value from the Low Pass Filter is compared to a Ground Key Detect High Threshold GKDH:HGKD[5:0] address (0x60) value. Hysteresis is enabled automatically by programming a second threshold GKDL:LGKD[5:0] address (0x61) to detect when the Ground Key is ...
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As the above figure illustrates, an 8-byte FIFO substantially reduces CPU intervention in generating FSK. Transmitted FSK data is placed in the FIFO by writing to the FSKTD:FSK[7:0] address (0x11) register. The writing process can be controlled by the status ...
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Tones can be directed either towards the line or the PCM interface by programming the RMPC:TRAP[7] bit address (0xC1). Frequency A (Volts) PK (Hz) 697 0.31 770 0.31 852 0.31 941 0.31 1209 ...
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DTMF DETECTION Dual Tone Multi Frequency (DTMF) tones consist of a low tone of 697Hz, 770Hz, 852Hz or 941Hz and high tone of 1209Hz, 1336Hz, 1477Hz or 1633Hz. The incoming signal is separated into high-group and low-group tones, and ...
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CODEC The N681386/87 converts the analog transmit signal into a PCM code, either by using µ-Law, A-Law or linear PCM, and vice versa. A-Law, µ-Law and PCM encoding and decoding is performed according to the recommendations in the ITU-T ...
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Conversely, to calculate the dB value of the gain based on known gain step values, the equation is: The table below contains a sample of possible gain settings. dB -∞ -24 - Table 23: Digital Gain Adjust ...
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HB address (0x41). This register can also be used to disable the Tran hybrid balancing completely. It should also be noted that Tran hybrid Balance adjustments are independent of ...
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Country India, New Zealand Germany (Legacy) UK (Legacy) Australia Table 25: Examples of Complex Impedance Matching Complex Impedance Settings are realized using the Impedance Matching Coefficients loaded into IMRAM 0xF3 using control functions in IMCTRL 0xF5. In this case IM1:ZR1[3:0] ...
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TESTING The N681386/87 includes extensive test and diagnostics features. available through the several voltages and current registers. GR-909 line test capabilities can also be supported. In addition five loop back test options, three digital loop backs (DLP1, DLP2 and ...
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DIAGNOSTICS SUPPORT The N681386/87 provides a variety of registers which proved both voltages and current values from the line which are either measured or calculated (see tables 7 and 8). These registers are updated at a rate of 800 ...
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Figure 21 for example, if the device is operating in the constant voltage region the V V and combination of coarse and fine adjustments ensures rapid convergence on the target voltage Two different DC/DC conversion ...
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The Figure below illustrates how voltage regulation occurs in the Forward Active state BATL BATL VOV:TR Figure 21: Voltage Tracking in Forward Active State The values for and V are set ...
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EXTERNAL BATTERY SWITCHING The N681386/87 device can also operate from two or three external battery supplies. The external battery supply architecture can be enabled by pulling the XBAT Pin HIGH. This will also power down the on-chip PWM controllers. ...
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DIGITAL INTERFACE 12.2.1. CLOCK GENERATION The N681386/87 will generate the necessary internal clock frequencies from the BCLK input. BCLK must be synchronous to the 8 kHz frame sync clock and run at one of the following rates: Binary Clock ...
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PCM INTERFACE N681386/87 supports a flexible PCM interface structure which can be configured to perform multiple industry standard PCM modes. Data is received serially through the PCMR pin and transmitted serially through the PCMT pin. Timeslots for data transmission ...
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The PCMT pin is high impedance except for the duration of the PCM transmit. PCMT will return to high impedance either on the negative edge of BCLK during the LSB the positive edge of BCLK following the LSB ...
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TOGGLING BETWEEN WIDEBAND AND NARROWBAND It is not recommended to toggle between Wideband and Narrowband when 16kHz frame sync is used, since it could unlock the PLL. However, the architecture may allow it when the pin is toggled at ...
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PCM INTERFACE 16KHz FRAME SYNC During Wideband operation and 16kHz frame sync the PCM data will be transmitted and received as one sample per frame sync. The location of the MSB of each sample on the PCM bus with ...
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SERIAL PERIPHERAL INTERFACE (SPI) The Serial Peripheral Interface (SPI) is one of the widely accepted communication interfaces implemented in Nuvoton’s Pro-X portfolio. SPI is a software protocol allowing operation on a simple 4-wire bus where the data is transferred ...
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Bit Bit Description Location 1 Control bit to select 12-Bits monitoring This is a channel selection bit. In case of a single channel 2 device this bit must be set to “0” Must be set to “0” ...
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Figure 27: Register write operation through a 8-bit SPI port Figure 28: Register read operation through a 8-bit SPI port Figure 29: Register write operation through a 16-bit SPI port Figure 30: Register read operation through a 16-bit SPI port ...
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SPI DAISY CHAIN When using multiple N681386/87 devices, SPI programming can be accomplished using a daisy chain architecture which allows all chips to share one CSb and one SCLK. To enable the daisy chain configuration, the DSY pin should ...
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Figure 33: DATA for Three Device Daisy Chain application 12.2.6. SPI BURST MODE The N681386/87 also supports a burst mode which allows multiple consecutive registers to be written to or read using a single Device address and Register address with ...
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SPECIAL READ SEQUENCE FOR 12-BIT WIDE REGISTER Although N681386/87 has 8-bit wide register map, it includes some additional register bits for accurate ADC monitoring. N681386/87 includes a special SPI Read feature. This read feature allows the user to read ...
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CSb DEVICE ADDRESS SCLK SDI SDO CSb DEVICE ADDRESS SCLK 1 SDI SDO 12-bit Read data Figure 35: SPI 12-bits Read ...
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INTERRUPT HANDLING A number of events are capable of generating an interrupt. However, an interrupt signal is generated only if the bit corresponding to that particular interrupt event is enabled in the Interrupt Enable Register. corresponding bit is set ...
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GENERAL DESCRIPTION FOR N681622 (LINEFEED CIRCUIT) The N681622 is the first supporting chip of its kind in the Nuvoton’s Pro-X line of products. It integrated the high voltage linefeed circuit. It can be used with N681386, N681387, N682386 and ...
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REGISTER DESCRIPTION Please refer to the SPI command description to read and write instruction. For maximal forward compatibility recommended that “0” be written to reserved bits. “ RES ” in the register map means Reserved. ASYNC means ...
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Addr Addr D7 Name (Dec) (Hex DTMFEN ADCOSEL DTMFCTRL1 49 31 DTMFCTRL2 50 32 DTMFCTRL3 51 33 DTMFST 52 34 DTMFTHRH 53 35 DTMFTHRL 54 36 DTMFPDT 55 37 DTMFADT 56 38 DTMFACT 58 3A DTMFRDY DTMFST DTMFRDT ...
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Addr Addr D7 Name (Dec) (Hex) 120 78 RTMNT 121 79 LCMNT 122 7A MNT5 123 7B MNT7 124 7C MNT9 125 7D MNT11 126 7E MNT13 127 7F MNT15 128 80 BATV 129 81 VTIP 130 82 VRING 131 ...
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Addr Addr D7 Name (Dec) (Hex) 172 AC CC 173 AD OS2RPD 175 AF CAL1 176 B0 CAL2 177 B1 CAL3 180 B4 HISENSE BTVR IQTROS 181 B5 PWCT 182 B6 CAL4 192 C0 OSN 193 C1 TRAP LBAC RMPC ...
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Addr Addr D7 Name (Dec) (Hex) 244 F4 IMDEL 245 F5 IMEN 246 F6 PCMSCAL 247 F7 PCMSCAH 248 F8 249 F9 250 FA 251 FB IMEN Decimal to Hex Conversion To convert decimal value to hex value divide the ...
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PCM CONTROL REGISTERS 14.1.1. PCM CONTROL REGISTER Addr. Name D7 D6 CMS[1:0] 0x00 PCMC The following table explains the PCM control register bits. Bit Bit Description Location 0 PCM path including digital receive path 2 Tri-state PCMT LSB 3 ...
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PLL STATUS REGISTER Addr. Name D7 D6 PLLCM CLK1544EN 0x04 PLLS PL[0] and BCFS[4:1] are status bits which means they are READ ONLY bits in this register. Any write to these bits will be ignored. FSRATE[5], CLK1544EN[6], and PLLM[7] ...
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PCM FREQUENCY SETTING REGISTER Addr. Name D7 D6 BCF[3:0] 0x05 PCMFS The following table explains the PCM Frequency Setting register bits. Bit Bit Description Location 0 Soft Reset 1 Band Select 2 Frame Sync Source 3 Internal Frame Sync ...
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SILICON VERSION ID REGISTER (READ ONLY) Addr. Name D7 0x06 SIREV Silicon revision ID Register is a READ ONLY register. 14.1.6. DEVICE VERSION ID REGISTER (READ ONLY) Addr. Name D7 0x07 DVID Device Version ID Register is a READ ...
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FSK REGISTERS 14.2.1. FSK CONTROL REGISTER Addr. Name D7 D6 PEN PE 0x10 FSKC The following table explains the FSK Control Register bits. Bit Bit Description Location 0 FSK Encoder 1 FSK Specification 2 Number of STOP bits FSK ...
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FSK STATUS REGISTER (READ ONLY) Addr. Name D7 0x12 FSKS “ RES ” in the register map means reserved bit(s). FSK Status Register is a READ ONLY register. The following table explains the FSK Status Register bits. Bit Bit ...
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FSK TCR REGISTER Addr. Name D7 D6 0x14 FSKTCR “ RES ” in the register map means reserved bit(s). Bit Bit Description Location 0 Fast Mode 1 FSK Route Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC ...
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DIAGNOSTIC REGISTERS 14.3.1. DIAGNOSTIC CONTROL 0 Addr Name D7 D6 FIFOIP DCREN 0x15 DIAGCTRL0 Bit Bit Description Location 0 Enable Diagnostic Mode 2 Converts unsigned Source Register data to signed data 3 Enable DIAGFIFO0 / DIAGFIFO1 FIFO Structure. Enable ...
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Select AC/DC source for Diagnostics ACSEL2 DCSEL2 14.3.3. DIAGNOSTIC CONTROL AND 5 Addr. Name D7 0x17 DIAGCTRL2 0x18 DIAGCTRL3 RES 0x19 DIAGCTRL4 DCRDC DCRAC 0x1A DIAGCTRL5 Select MADC source ...
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Bit Bit Description Location 5 DC Removal RC Time Constant 6 DC Removal Accelerated Convergence. Enable DC Removal output to DC Path LPF in addition to the 7 normal connection to the AC Path LPF DIACNTRL0:DCREN must be set. Notes: ...
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DIAGNOSTIC CONTROL 8 (READ ONLY) Addr. Name D7 0x1D DIAGCTRL8 DCDP[11:0]: DC Diagnostic Path Output ACDP[11:0]: AC Diagnostic Path Output NOTE: This register is structured to be read in 4 byte burst 14.3.6. DIAGNOSTIC FIFO 0 AND FIFO1 (READ ...
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SYSTEM REGISTERS 14.4.1. PCM HPF (HIGH PASS FILTER) Addr. Name D7 D6 DACLP 0x20 PHF RES “ RES ” in the register map means reserved bit(s). Bit Bit Description Location 0 PCM Transmit HPF (DAC) 1 PCM Receive HPF ...
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POWER ON Addr. Name D7 D6 CDCC 0x22 PON “ RES ” in the register map means reserved bit(s). The following table explains the Loop Back Control Register bits. Bit Bit Description Location 0 DC/DC Power Control Circuitry 1 ...
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LINEFEED TRIM Addr Name D7 D6 ZCPINV ZCPEN 0x23 ILIM Bit Bit Description Location Ring Limiting Gain Adjust strength of Ring 2 limiting Impacts noise 3 Idle State Battery Current Idle State Battery Current Stops RIP in idle 4 ...
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INTERRUPT REGISTERS 14.5.1. INTERRUPT VECTOR LOW (READ ONLY) Addr. Name D7 D6 0x24 INTV “ RES ” in the register map means reserved bit(s). Interrupt Vector Register is a READ ONLY register. Each bit in this register will be ...
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INTERRUPT ENABLE REGISTER 1 Addr Name D7 D6 PAT3E PAR3E 0x27 IE1 This register enables all the Power Alarm and the Loop Closure interrupt of the device. An interrupt can be enabled by writing a HIGH “1” in the ...
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INTERRUPT ENABLE REGISTER 2 Addr. Name D7 D6 FSKIE DTMFIE 0x29 IE2 Bit Bit Description Location 0 Oscillator 1 Active Timer 1 Oscillator 1 Inactive Timer 2 Oscillator 2 Active Timer 3 Oscillator 2 Inactive Timer 4 Ringing Active ...
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INTERRUPT ENABLE REGISTER 3 Addr. Name D7 D6 0x2B IE3 RES “ RES ” in the register map means reserved bit(s). This register enables the dice Temperature interrupt of the device. An interrupt can be enabled by writing a ...
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DTMF DETECTION REGISTER 14.6.1. DTMF CONTROL 1 Addr. Name D7 DTMFEN ADCOSEL 0x30 DTMFC1 ADC output is the signal from ADC coming to DTMF decode. Therefore, the ADC Select bit select either the ADC or PCM input to the ...
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Time constant used for DTMF frequency estimation DTMFTC3 DTMFTC2 14.6.2. DTMF CONTROL 2 Addr. Name D7 D6 0x31 DTMFCTRL2 “ RES ” in the register map means reserved bit(s). Bit Bit Description Location 0 ...
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DTMF STATUS (READ ONLY) Addr. Name D7 D6 0x33 DTMFST “ RES ” in the register map means reserved bit(s Read ONLY bit Bit Bit Description Location 0 DTMF buffer is empty 14.6.5. DTMF THRESHOLD Addr. ...
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DTMF ABSENT DETECT TIME Addr. Name D7 D6 0x37 DTMFADT The time for which a tone must be absent before a Range 14.6.8. DTMF ACCEPT TIME Addr. Name D7 D6 0x38 DTMFACT Range This guard time improves detection performance ...
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DTMF RECEIVE DATA STATUS Addr. Name D7 DTMFRDY 0x3A DTMFRDT “ RES ” in the register map means reserved bit(s). DTMF Detector received data, DTMFRDT[3:0]. This data is valid when DTMF Ready, DTMFRDY[7], is active. Bit Bit Description Location ...
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DTMF COLUMN FREQUENCY Addr. Name D7 D6 0x3D DTMFCFH 0x3E DTMFCFL These two bytes are for debug mode, and display the DTMF Column frequency directly. • DTMFCF[15:3] is the integer part of the DTMF Column frequency, • DTMFCF[2:0] ...
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LINE REGISTERS 14.7.1. AC PATH GAIN Addr. Name D7 D6 RAMP PREN 0x40 APG Analog Receive Gain ARX1 ARX0 Gain ( Mute Bit Bit Description Location 5 ...
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COMMON RINGING BIAS ADJUST DURING RINGING Addr. Name D7 D6 0x42 VCMR RES “RES” in the register map means reserved bit(s). The above register sets Common Ringing Bias Adjustment voltage during Ringing. To convert decimal value to hex value ...
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LINEFEED STATUS Addr. Name D7 D6 SLS[3:0] 0x44 LS LS3 LS2 LS:LS[3:0] is the Linefeed Status Register ...
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LGCM1 Bit Bit Description Location 6 Series Resistor with CRn 7 Series Resistor with CTn 14.7.7. RING TRIP DETECT STATUS/ LOOP CLOSURE STATUS (READ ONLY) Addr. Name D7 D6 RTM LCM 0x46 RTLC “ RES ” ...
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LOOP CLOSURE DEBOUNCE Addr. Name D7 0x47 LCDB Loop Closure Detect Debounce Interval LCDI[7: 8-bit register which sets time interval (decimal value) in digital format. To convert decimal value to hex value please refer to the beginning ...
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DC/DC CONTROLLER CONTROL Addr. Name D7 0x4A DDCC This register sets DC/DC Converter Minimum OFF Time. Use the following equation to calculate the period. DCOFF[7:0] should be programmed to values ≥ 04 hex The PLL Period (expressed in nsec) ...
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GROUND MARGIN VOLTAGE Addr. Name D7 UBR 0x4D GMV “ RES ” in the register map means reserved bit(s). Minimum Range Bit Bit Description Location 7 Unbalanced Ringing 14.7.14. HIGH BATTERY VOLTAGE Addr. Name D7 XBATR 0x4E VBHV “ ...
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LOOP CLOSURE DETECT/RING TRIP DETECT COEFFICIENT Addr. Name 0x50 LCDCL 0x51 RTDFCLD 0x52 DCHD Loop Closure Detect Coefficient LCDC[11:0] is governed by the cutoff frequency f AC Ring Trip Detect Filter Coefficient ARTDFC[11:0] is governed by the cutoff frequency ...
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RING TRIP DETECT THRESHOLD Addr. Name D7 0x55 RTTA RES Range 14.7.19. OFFSET VOLTAGE Addr. Name D7 0x56 VOV “ RES ” in the register map means reserved bit(s). The Tracking Mode is enabled by set TR bit HIGH ...
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DAC/ADC AUTOMUTE FUNCTION Addr. Name D7 D6 AMTEN AMTSEL 0x5E AUTOMT Bit Bit Description Location 6 Automute Select 7 Automute Enable Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC AMTTHR Bit Value Bit Name 0 DAC ...
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GROUND KEY DETECTION 14.8.1. LINEFEED CONTROL Addr. Name D7 D6 ASQH 0x5F XBTC RES “ RES ” in the register map means reserved bit(s). Bit Bit Description Location 2 DC Bias Current OFF-Hook 3 DC Bias Current On-Hook TR ...
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GROUND KEY DETECT DEBOUNCE TIME Addr. Name D7 0x62 GKDDT Range 14.8.4. GROUND KEY DETECT FILTER COEFFICIENT LOW/ HIGH Addr. Name D7 0x63 GKDFCL GKDEN 0x64 GKDFCH Ground Key Detection Filter Coefficient governs the Ground Key Detect LPF cutoff ...
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DC RING TRIP CURRENT THRESHOLD Addr. Name D7 0x67 RTTD RES DC Ring Trip current Threshold in Internal Ringing Mode Range 14.8.7. DC RING TRIP DEBOUNCE TIME Addr. Name D7 D6 0x68 RTDBD Range Preliminary Datasheet Rev1.0 Single Programmable ...
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EXTERNAL BATTERY SWITCH OUTPUT CONFIGURATION 1 Addr. Name D7 D6 0x6A XBSDCN 0x6B XBSDCP External battery switch DCN pin and DCP output configuration for different line states Linefeed State Open Open Forward/Reverse Active Forward/Reverse Active Forward/Reverse ON-HOOK Transmission Forward/Reverse ...
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DC/DC TARGET VOLTAGE (READ ONLY) Addr. Name D7 0x77 DCTR In Inductor mode the Target Voltage for DC/DC Converter is a READ ONLY register. Minimum Range Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC VTR[7:0] ...
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MONITORING REGISTERS 14.9.1. MONITOR CURRENT FOR RING TRIP AND LOOP CLOSURE Addr Name Bit7 Bit6 (Hex) 78 RTMNT 79 LCMNT Minimum Range 14.9.2. MONITOR CURRENT FOR RING TRIP AND LOOP CLOSURE Addr Name Bit7 Bit6 (Hex) 7A MNT5 7B ...
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LINE CONTROL REGISTERS 14.10.1. VOLTAGE REGISTERS 14.10.1.1. BATTERY VOLTAGE SENSE (READ ONLY) Addr. Name D7 0x80 BATV Battery Voltage VB[7: READ ONLY register. Range 14.10.1.2. TIP/RING VOLTAGE SENSE (READ ONLY) Addr. Name D7 D6 VTIP 0x81 VTIP[3:0] ...
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TRANSISTOR CURRENT REGISTERS (TIP/RING TRANSISTOR 1/2/3 CURRENT SENSE) Addr. Name D7 D6 QT3I 0x85 QT3I (XP) QT3I[3:0] QR3I 0x86 QR3I (XP) QR3I[3:0] QT1I 0x87 QT1I (XP) QT1I[3:0] QT2I 0x88 QT2I (XP) QT2I[3:0] QR1I 0x89 QR1I (XP) QR1I[3:0] QR2I 0x8A ...
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LOOP SUPERVISION 14.12.1. LONGITUDINAL CURRENT Addr. Name D7 D6 LGI 0x8C LGI (XP) “XP” stands for extra precision register. The range value depends on calibration. The values provided for Range is without any calibration. Please refer to the SPI ...
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TIP, RING, AND LOOP CURRENT (READ ONLY) Addr. Name D7 TIPI 0x8E ITLP[3:0] (RO) TIPI (XP) RINGI 0x8F IRLP[3:0] (RO) RINGI (XP) LPI 0x90 ILP[3:0] (RO) LPI (XP) “XP” stands for extra precision register. The above registers are READ ...
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COMMON MODE VOLTAGE Addr. Name D7 D6 SCM 0x92 SCM[3:0] SCM (XP) “XP” stands for extra precision register. The Common Mode Voltage is calculated using the equation below. Please refer to the SPI Peripheral Interface section for details. 14.12.6. ...
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RING EMITTER VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY) Addr. Name D7 0x95 VEQR1 This is the emitter sense of the transistor QR1 which is used for the power alarm computation. This register is a READ ONLY register. The ...
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PEAK TO PEAK LOOP VOLTAGE (READ ONLY) Addr. Name D7 VLPP2P 0x9B LPVP2P[3:0] (RO) VLPP2P (XP) “XP” stands for extra precision register. This read only register captures the peak-to-peak loop voltage. The peak detector circuit clears this register value ...
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POWER ALARM LPF POLE REGISTERS 14.13.1. POWER ALARM COUNTER Addr. Name D7 0x9F PALCNT The Power Alarm Counter indicates the number of rising edges of the LOWVDC or HIGHIDC flags. The value of this register clips at 255. This ...
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POWER ALARM THRESHOLD FOR TRANSISTOR 1-3 Addr. Name D7 D6 0xA5 PATHQ2 0xA6 PATHQ1 0xA7 PATHQ3 DESCRIPTION CONDITION Dependent on the QT1 and QR1 maximum power dissipation rating QT2 and QR2 of the external transistors QT3 and QR3 14.14. ...
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TEMPERATURE ALARM THRESHOLD Addr Name D7 D6 0xAA THAT T = TATH[7:0] – 14.14.2. LOOP CLOSURE MASK COUNT Addr Name D7 D6 0xAB LCMCNT Range 14.14.3. COARSE CALIBRATION INTERNAL RESISTOR Addr Name D7 D6 0xAC CC RES ...
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CALIBRATION Addr Name D7 D6 SDAT[3:0] 0xAF CAL1 TVTE1[3:0] 0xB0 CAL2 SCMT[3:0] 0xB1 CAL3 All values are trim parameters which can be used during the calibration sequence. Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC VBATT[3:0] ...
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DC OFFSET REGISTERS 14.16.1. DC OFFSET (RING, TIP, AND VBAT) Addr. Name D7 HISENSE 0xB4 IQTROS “ RES ” in the register map means reserved bit(s). All values are trim parameters which can be used during the calibration sequence. ...
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TONE GENERATION REGISTERS 14.17.1. OSCILLATOR CONTROL Addr. Name D7 D6 0xC0 OSN RES “ RES ” in the register map means reserved bit(s). Bit Bit Description Location 0 Oscillator 1 1 Oscillator 2 4 Oscillator n Zero-Crossing 5 Oscillator ...
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OSCILLATOR 1 AND 2 COEFFICIENT LOW/HIGH Addr. Name D7 0xC6 OS1CL 0xC7 OS1CH 0xC8 OS2CL 0xC9 OS2CH Coefficient for Oscillator m (OmC[15:0] m=1, and 2, refer to Tone Generation see section for the formula. OS2CL is 18-bits long word. ...
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GENERAL TONE GENERATION 14.19.1. RING OFFSET Addr. Name D7 D6 O2C[1:0] 0xDC ROFFS “RES” in the register map means reserved bit(s). TIP to RING Offset for Ringing, Sets DC Offset component to the Ringing Waveform Minimum Range 14.19.2. ADC/DAC ...
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PWM DC/DC FINE TUNING Addr. Name D7 D6 0xE0 ST0L0 0xE1 ST1L0 RES 0xE2 ST2L0 RES 0xE3 ST0L1 0xE4 ST1L1 RES 0xE5 ST2L1 RES “ RES ” in the register map means reserved bit(s). Name Addr. Symbol Stepsize 0xE0 ...
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PWM DC/DC FINE TUNING Addr. Name D7 D6 0xEC WM0 RES 0xED WM1 RES 0xEE WM2 RES PWMTC 0xEF XSTEP “ RES ” in the register map means reserved bit(s). “n” is the number written to the register in ...
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IMPEDANCE MATCH REGISTER 14.19.6.1. IMPEDENCE MATCHING COEFFICIENT RAM Addr. Name D7 D6 0xF3 IMRAM Read and Write location for the Impedance Matching Coefficient RAM. Used in conjunction with Write Sequence described in IMCTRL 0xF5. 14.19.6.2. IMPEDANCE MATCHING DELAY COUNT ...
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PCM SCALING Addr. Name D7 D6 0xF6 PCMSCAL 0xF7 PCMSCAH Bit PCMSCA[15:0] 14.19.6.5. RESERVED REGISTERS Addr. Name D7 D6 0xF8 0xF9 0xFA These three register must be set to 0x00 during a write operation 14.19.6.6. FILTER BYPASS Addr. Name ...
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TIMING DIAGRAM 15.1. PCM TIMING DIAGRAM FOR NON-GCI SYMBOL DESCRIPTION 1/T FS Frequency Minimum LOW Width FSL 1/T BCLK, BCLK Frequency BCK T BCLK HIGH Pulse Width BCKH T BCLK LOW Pulse Width BCKL T ...
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PCM TIMING DIAGRAM FOR GCI SYMBOL DESCRIPTION 1/T FS Frequency FS 1/T BCLK Frequency BCK T BCLK HIGH Pulse Width BCKH T BCLK LOW Pulse Width BCKL T BCLK Falling Edge to FS Rising Edge Hold Time FRH ...
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SYMBOL DESCRIPTION 1/T BLCK Clock Frequency BCK T BLCK Period Jitter Tolerance jitter BCLK Duty Cycle for 256 kHz Operation BCKH BCK Minimum Pulse Width HIGH for BCLK(512 kHz or T BCKH Higher) Minimum Pulse Width LOW ...
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SPI TIMING DIAGRAM \CS T CSS SCLK SDI T SDOD SDO T SDOA Figure 39: SPI Timing (Non-Daisy Chain Mode) SYMBOL DESCRIPTION T SCLK Cycle Time SCK T SCLK High Pulse Width SCKH T SCLK Low Pulse Width SCKL ...
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Figure 40: In-band Transmit Frequency Response Figure 41: In-band Receive Frequency Response Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 145 of 164 N681386/87 January 2010 ...
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Figure 42: Transmit Group Delay Distortion Figure 43: Receive Group Delay Distortion Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 146 of 164 N681386/87 January 2010 ...
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Figure 44: 2-Wire to PCM Signal to Distortion Mask (A-Law) Figure 45: 2-Wire to PCM Signal to Distortion Mask (µ-Law) Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 147 of 164 N681386/87 January 2010 ...
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Figure 46: Wideband In-band Transmit Frequency Response Figure 47: Wideband Transmit Group Delay Distortion Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 148 of 164 N681386/87 January 2010 ...
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Figure 48: Wideband Receive Group Delay Distortion Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 149 of 164 N681386/87 January 2010 ...
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DIGITAL I/O 16.1.1. µ-LAW ENCODE DECODE CHARACTERISTICS Normalized Encode D7 D6 Decision Levels Sign Chord 8159 1 0 7903 : 4319 1 0 4063 : 2143 1 0 2015 : 1 0 1055 991 511 479 ...
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A-LAW ENCODE DECODE CHARACTERISTICS Normalized Encode Decision Sign Chord Chord Levels 4096 3968 : 2176 2048 : 1088 1024 : 544 512 : 1 ...
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A-LAW CODES FOR 0DBM0 OUTPUT (DIGITAL MILLIWATT) µ-Law Sample Sign bit Chord bits (D7) (D6,D5,D4 001 2 0 000 3 0 000 4 0 001 5 1 001 6 1 000 7 1 000 8 ...
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TYPICAL APPLICATION CIRCUITS 17.1. DC/DC APPLICATION Figure 49: Typical Application Block Diagram Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 153 of 164 N681386/87 January 2010 ...
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DISCRETE LINE DRIVER Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Figure 50: Discrete Line-driver Page 154 of 164 N681386/87 January 2010 ...
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DC DC Figure 51: Inductor based circuit 12V supply Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 155 of 164 N681386/87 January 2010 ...
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TRIPLE BATTERY SWITCH APPLICATION 1 2 Figure 52: Triple Battery based Switch 1 Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 156 of 164 N681386/87 January 2010 ...
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N681386/87 DCDC APPLICATION USE WITH SLFC N681622 Figure 53: N681386/87 Pro-X Application diagram to be used with N681622 Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 157 of 164 N681386/87 January 2010 ...
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N681622 LINEFEED CIRCUIT Figure 54: N681622 Linefeed circuit Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 158 of 164 N681386/87 January 2010 ...
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PACKAGE SPECIFICATION 18.1. LQFP-48 (10X10X1.4mm FOOTPRINT 2.0mm) Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 159 of 164 N681386/87 January 2010 ...
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QFN-48 Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 160 of 164 N681386/87 January 2010 ...
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QFN 20L 4X4 mm , PITCH:0.50 mm Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Page 161 of 164 N681386/87 January 2010 ...
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... When ordering N681386/87 series devices, please refer to the following part numbers: Part Number N681386DG N681387DG N681386YG N681387YG N681622_ _ Product Family When ordering N681622 series devices, please refer to the following part numbers: Part Number N681622YG Preliminary Datasheet Rev1.0 Single Programmable Extended Codec/SLCC Package Material: Pb-free Package G = Package Type: = LQFP-48 ...
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VERSION HISTORY VERSION DATE PAGE January 77 & 96 V0.85 2010 86 88 & 102 -103 105 134 135 18 – ...
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VERSION DATE PAGE 93 94 107 111 115 122 - 128 129 131 136 139 153 Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control ...