N681622YG Nuvoton Technology Corporation of America, N681622YG Datasheet - Page 72

• Manufacturer Part Number: N681622YG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of N681622YG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

N681386/87
Single Programmable Extended Codec/SLCC
Figure 33: DATA for Three Device Daisy Chain application
12.2.6. SPI BURST MODE
The N681386/87 also supports a burst mode which allows multiple consecutive registers to be written to or read
using a single Device address and Register address with BST=1. The complete register address space (256
locations) can be read/ written to using burst mode.
CSb
16 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
(8 Bit CMD + 8 Bit Address )
BST = 1
Figure 34: Burst mode operation (BST=1)
The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher address after each byte of data is shifted out. When the
highest address is reached, the address counter rolls over to address (0x00) allowing the read cycle to be continued
indefinitely.
When the BST bit in Device address is set during a write operation the N681386/87 will accept multiple 8-bit DATA
blocks which will be written to sequential address locations beginning with the address specified in Register address.
The length of the burst is determined by the Chip Select (CSb). Note that if there is a location within the sequence
without a register assignment a dummy byte should be sent at the corresponding location in the DATA sequence.
Similarly during a burst read operation the device will output DATA as long as CSb is LOW. The device will output a
dummy byte (0x00) when locations without register assignments are within the sequence.
Register bits
PCMC:BDAEN[3] address (0x00) and PCMC:BCEN[1] address (0x00) is be used to determine the broadcasting
preferences. By default, after a reset, the device will accept all burst write commands without decoding bits C3 to C6.
Once the PCMC:BCEN[1] address (0x00) bit is set, the device will only accept burst write data for the channel. Once
the PCMC:BDAEN[3] address (0x00) bit is set, the device will only accept burst write data when C3 to C6 are ‘0’.
Preliminary Datasheet Rev1.0
Page 72 of 164
January 2010