N681622YG Nuvoton Technology Corporation of America, N681622YG Datasheet - Page 63

• Manufacturer Part Number: N681622YG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of N681622YG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The N681386/87 will generate the necessary internal clock frequencies from the BCLK input. BCLK must be
synchronous to the 8 kHz frame sync clock and run at one of the following rates:
The frame sync can either be supplied externally or it can be generated internally by the N681386/87, by setting the
PCMFS:FSS[2] address (0x05) bit to “1”. If frame sync is supplied externally (PCMFS:FSS=0), the ratio of the BCLK
rate to the frame sync rate is determined via a counter clocked by BCLK which can be read at the PLLS:BCFS[4:1]
address (0x04). This value is used to control the internal PLL, which multiplies BCLK appropriately to generate the
internal clock frequency required to run the internal circuitry.
If the frame sync is supplied internally (PCMFS:FSS=1), the user must set PCMFS:BF[3:0] to indicate BCLK so that
an appropriate multiple is calculated to generate the required internal frequency. If the frame sync is generated
internally its width can be selected by programming PCMFS:IFST[3] address (0x05).
Preliminary Datasheet Rev1.0
1-bit clock long (for Short Frame Sync, GCI and IDL modes)
8-bit clocks long (for 8-bit Long Frame Sync mode)
12.2. DIGITAL INTERFACE
12.2.1. CLOCK GENERATION
Binary Clock
8.192 MHz.
1.024 MHz
1.152 MHz
1.536 MHz
1.544 MHz
2.048 MHz
4.096 MHz
256 kHz
512 kHz
768 kHz
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Single Programmable Extended Codec/SLCC
Decimal Clock
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
N681386/87
January 2010