N681622YG Nuvoton Technology Corporation of America, N681622YG Datasheet - Page 58

• Manufacturer Part Number: N681622YG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of N681622YG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

N681386/87
Single Programmable Extended Codec/SLCC
12.1.7. TESTING
The N681386/87 includes extensive test and diagnostics features.
Real-time DC linefeed measurements are
available through the several voltages and current registers. GR-909 line test capabilities can also be supported. In
addition five loop back test options, three digital loop backs (DLP1, DLP2 and DLP3) and two analog loop backs
(ALP1, ALP2) are available. Figure 3, details the AC path architecture and also indicates the precise locations of the
test loop backs.
12.1.7.1.
LOOP BACK TESTS
The full analog loop back LB:ALP2[4] address (0x21) allows the testing of almost all the circuitry of both transmit and
receive paths. The compressed 8-bit/16-bit linear transmit data stream is fed back serially to the input of the receive
path expander. The signal path starts with the analog signal at the input of the transmit path and ends with an analog
signal at the output of the receive path. LB:ALP1[3] address (0x21) takes the digital stream at the output of the A/D in
the transmit path and feeds it back to the input of the D/A in the receive path. As with LB:ALP2[4] address (0x21) the
signal path starts with the analog signal at the input of the transmit path and ends with an analog signal at the output
of the receive path.
Full digital loop back LB:DLP1[0] address (0x21) tests practically all transmit and receive path circuitry. The analog
signal at the output of the receive path is fed back to the input of the transmit path by way of the Trans-hybrid filter
path. The Trans-hybrid balance may be set to unity gain so that the return signal is not attenuated. A switch in the
receive path is opened when this loop is selected so that no signal appears on the line during this loop back. The
signal path starts with 8-bit/16-bit PCM data input to the receive path and ends with 8-bit/16-bit PCM data at the
output of the transmit path. The user can bypass the companding process and interface directly to the 16-bit data.
LB:DLP2[1] address (0x21) takes the digital stream at the input of the D/A in the receive path and feeds it back to the
output of the A/D in the transmit path. The signal path starts with 8-bit/16-bit PCM data input to the receive path and
ends with 8-bit/16-bit PCM data at the output of the transmit path. This loop back option allows the testing of the
digital signal processing circuitry of the N681386/87 independent of any analog signal processing activity. DLP3
loops the digital data stream just beyond the PCM interface, taking the 8-bit/16-bit output of the PCM receive
interface and looping directly to the input of the PCM transmit interface.
Preliminary Datasheet Rev1.0
Page 58 of 164
January 2010