PIC24FV32KA304-I/PT Microchip Technology, PIC24FV32KA304-I/PT Datasheet - Page 191

MCU 32KB FLASH 2KB RAM 44-TQFP

PIC24FV32KA304-I/PT

Manufacturer Part Number
PIC24FV32KA304-I/PT
Description
MCU 32KB FLASH 2KB RAM 44-TQFP
Manufacturer
Microchip Technology
Datasheets

Specifications of PIC24FV32KA304-I/PT

Processor Series
PIC24FV
Core
PIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-44
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Part Number:
PIC24FV32KA304-I/PT
Manufacturer:
Microchip Technology
Quantity:
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19.2.4
REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER
 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
Note 1:
RTCEN
R/W-0
R/W-0
CAL7
2:
3:
(2)
The RCFGCAL register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
RTCC CONTROL REGISTERS
RTCEN: RTCC Enable bit
1 = RTCC module is enabled
0 = RTCC module is disabled
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
HALFSEC: Half Second Status bit
1 = Second half period of a second
0 = First half period of a second
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00 = MINUTES
01 = WEEKDAY
10 = MONTH
11 = Reserved
RTCVAL<7:0>:
00 = SECONDS
01 = HOURS
10 = DAY
11 = YEAR
R/W-0
CAL6
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
U-0
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
RTCWREN
R/W-0
R/W-0
CAL5
(2)
RTCSYNC
R-0, HSC
R/W-0
CAL4
PIC24FV32KA304 FAMILY
(3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HALFSEC
R-0, HSC
R/W-0
CAL3
(3)
RTCOE
R/W-0
R/W-0
CAL2
x = Bit is unknown
RTCPTR1
R/W-0
R/W-0
CAL1
(1)
DS39995B-page 191
RTCPTR0
R/W-0
R/W-0
CAL0
bit 8
bit 0

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