LMH2190TM-38/NOPB National Semiconductor, LMH2190TM-38/NOPB Datasheet - Page 13

• Manufacturer Part Number: LMH2190TM-38/NOPB
• Description: IC CLOCK QUAD 26MHZ DVR 16-USMD
• Manufacturer: National Semiconductor
• Type: Fanout Buffer (Distribution)r

Specifications of LMH2190TM-38/NOPB

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: No/No
• Input: Clock
• Output: Clock
• Frequency - Max: 27MHz
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-MicroSMD
• Frequency-max: 27MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH2190TM-38TR

CLOCK REQUEST LOGIC
The clock request logic enables an independent control of the
clock tree driver outputs (CLK1 to CLK4) as well as an overall
source clock request (SCLK_REQ) and LDO enabling. Since
the clock request logic always needs to be active, it is supplied
by either the output of the LDO (V
ABLE. Further details about the selection between V
ENABLE can be found in the
TOR
Clock Request Inputs
A clock request input is provided for each clock output
8). This allows the peripheral device to control the LMH2190
when it wants to receive a clock. In case the peripheral device
does not have clock request functionality, the CLKx_REQ can
System Clock Request Output
In the typical mode of operation, the clock request output will
be enabled if one of the 4 CLK_REQ inputs is high
9). However, this can be overridden via the I
has a register bit that forces the output to be enabled, inde-
pendent of the CLK_REQ input. The polarity of the output can
section later in the datasheet.
(a) Outputs with Skew only
LOW DROPOUT REGULA-
OUT
) or by the external EN-
2
C interface which
FIGURE 7. Clock Outputs Timing
FIGURE 8. Clock Request Input
30083815
OUT
(Figure
(Figure
and
13
be wired to a logic high level to enable the clock output (in
default register setting). Alternatively, it can be controlled
through I
active high or active low. When the LDO is off, the clock re-
quest logic still need to be powered such that it can turn on
the LDO. This is why the ENABLE input is used to power the
Clock Request Logic in case the LDO is off. Although the
CLK_REQ logic is supplied with 1.8V LDO voltage (or EN-
ABLE), the CLKx_REQ input can tolerate voltages up to
V
To prevent glitches on CLK outputs, enabling of the outputs
is done synchronously. A latch is used to ensure that the CLK
outputs will be enabled on the falling edge of the source clock
input (SCLK_IN).
be controlled via I
whether the output is configured as push/pull, open drain or
open source.
For the open drain case, there needs to be an external resistor
that pulls the SCLK_REQ to a high level. This high level may
BAT
.
(b) Outputs with Skew and Inversion
2
C. The CLKx_REQ input can be configured to be
2
C (CLK_REQ Output Polarity) along with
30083819
30083816
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