LMH2190TM-38/NOPB National Semiconductor, LMH2190TM-38/NOPB Datasheet - Page 16

IC CLOCK QUAD 26MHZ DVR 16-USMD

LMH2190TM-38/NOPB

Manufacturer Part Number
LMH2190TM-38/NOPB
Description
IC CLOCK QUAD 26MHZ DVR 16-USMD
Manufacturer
National Semiconductor
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of LMH2190TM-38/NOPB

Number Of Circuits
1
Ratio - Input:output
1:4
Differential - Input:output
No/No
Input
Clock
Output
Clock
Frequency - Max
27MHz
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-MicroSMD
Frequency-max
27MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMH2190TM-38TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LMH2190TM-38/NOPB
Manufacturer:
NS
Quantity:
270
www.national.com
Transferring Data
Every frame on the SDA line must be eight bits long, with the
most significant bit (MSB) being transferred first. Each byte of
data has to be followed by an acknowledge bit. The acknowl-
edge related clock pulse is generated by the master. The
transmitter releases the SDA line (HIGH) during the acknowl-
edge clock pulse. The receiver must pull down the SDA line
during the 9th clock pulse, signifying an acknowledge. A re-
ceiver which has been addressed must generate an acknowl-
edge after each byte has been received.
After the START condition, the I
dress
an eight bit which is a data direction bit (R/W). For the eighth
bit, a “0” indicates a WRITE and a “1” indicates a READ. The
second byte selects the register to which the data will be writ-
ten. The third byte contains data to write to the selected
register.
(Figure
14). This address is seven bits long followed by
2
C master sends a chip ad-
FIGURE 15. Example I
FIGURE 16. Example I
16
Register changes take effect at the SCL rising edge during
the last ACK from slave. An example of a WRITE cycle is
given in
plished, a WRITE function must precede the READ function,
as shown in the Read Cycle waveform
2
2
C Write Cycle
C Read Cycle
Figure
FIGURE 14. I
15. When a READ function is to be accom-
2
C Chip Address
(Figure
30083823
16).
30083820
30083824

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