PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 173

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.8
PORTG is a 5-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISG and LATG.
PORTG is multiplexed with EUSART, LCD and
CCP/ECCP/Analog/Comparator/RTCC/Timer input func-
tions (Table 11-14). When operating as I/O, all PORTG
pins have Schmitt Trigger input buffers. The open-drain
functionality for the CCPx and UART can be configured
using ODCONx.
RG4 is multiplexed with LCD segment drives controlled
by bits in
RG4/SEG26/RTCC/T7XKI/T5G/CCP5/AN16/P1D/C3INC
pin. The I/O port function is only available when the
segments are disabled.
The RG5 pin is multiplexed with the MCLR pin and is
available only as an input port. To configure this port for
input only, set the MCLRE pin (CONFIG3H<7>).
TABLE 11-14: PORTG FUNCTIONS
 2010 Microchip Technology Inc.
RG0/ECCP3/
P3A
RG1/TX2/CK2/
AN19/C3OUT
Legend:
Pin Name
PORTG, TRISG and
LATG Registers
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
the
Function
ECCP3
C3OUT
LCDSE2
AN19
RG0
RG1
P3A
TX2
CK2
Setting
register
TRIS
0
1
0
1
0
0
1
1
1
1
1
x
I/O
and
O
O
O
O
O
O
O
I
I
I
I
I
as the
Type
ANA
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
—
Preliminary
LATG<0> data output.
PORTG<0> data input.
ECCP3 compare output and ECCP3 PWM output. Takes priority over
port data.
ECCP3 capture input.
ECCP3 PWM Output A. May be configured for tri-state during
Enhanced PWM shutdown events.
LATG<1> data output.
PORTG<1> data input.
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module); user must configure
as an input.
Synchronous serial clock input (EUSART module).
A/D Input Channel 19. Default input configuration on POR. Does not
affect digital output.
Comparator 3 output.
PIC18F87K90 FAMILY
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS bit
settings. The pin override value is not loaded into the
TRIS register. This allows read-modify-write of the TRIS
register without concern due to peripheral overrides.
EXAMPLE 11-7:
CLRF
BCF
CLRF
BANKSEL ANCON2
MOVLW
MOVWF
MOVLW
MOVWF
PORTG
CM1CON, CON
LATG
0F0h
ANCON2
04h
TRISG
Description
INITIALIZING PORTG
; Initialize PORTG by
; clearing output
; data latches
; disable
; comparator 1
; Alternate method
; to clear output
; data latches
; make AN16 to AN19
; digital
; Value used to
; initialize data
; direction
; Set RG1:RG0 as
; outputs
; RG2 as input
; RG4:RG3 as inputs
DS39957B-page 173