PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 333

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.4.7
In I
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 21-19). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
0 and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 21-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD. The SSPxADD BRG value of 0x00 is not
supported.
FIGURE 21-19:
TABLE 21-3:
 2010 Microchip Technology Inc.
Note 1:
CY
2
C Master mode, the Baud Rate Generator (BRG)
) on the Q2 and Q4 clocks. In I
16 MHz
2:
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
A minimum of 16 MHz F
BAUD RATE
(2)
2
C™ interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE w/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SCLx
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
4 MHz
F
2
CY
C Master mode, the
OSC
is required to get the 1 MHz I
SSPM<3:0>
Reload
Control
Preliminary
CLKO
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
8 MHz
CY
Reload
* 2
PIC18F87K90 FAMILY
21.4.7.1
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
BRG Down Counter
SSPxADD<6:0>
2
C specification (which applies to rates greater than
2
C.
BRG Value
Baud Rate and Module
Interdependence
0Ch
18h
1Fh
63h
09h
27h
02h
09h
03h
F
OSC
/4
(2 Rollovers of BRG)
2
C Master mode at
DS39957B-page 333
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)