PIC18F86K90-I/PT Microchip Technology, PIC18F86K90-I/PT Datasheet - Page 311

• Manufacturer Part Number: PIC18F86K90-I/PT
• Description: 64kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TRA
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F86K90-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.4
The MSSP module in I
master and slave functions (including general call
support), and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial Clock (SCLx) – RC3/SCK1/SCL1/SEG17
• Serial Data (SDAx) – RC4/SDI1/SDA1/SEG16 or
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 21-7:
 2010 Microchip Technology Inc.
Note:
SDAx
SCLx
or RD6/SEG6/SCK2/SCL2
RD5/SEG5/SDI2/SDA2
Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
I
2
C™ Mode
Read
Shift
Clock
MSb
SSPxADD reg
Address Mask
Stop bit Detect
Match Detect
SSPxBUF reg
SSPxSR reg
MSSPx BLOCK DIAGRAM
(I
Start and
2
2
C mode fully implements all
C™ MODE)
LSb
Write
Addr Match
Set, Reset
S, P bits
(SSPxSTAT reg)
Internal
Data Bus
Preliminary
PIC18F87K90 FAMILY
21.4.1
The MSSP module has seven registers for I
operation. These are:
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Control Register 2 (SSPxCON2)
• MSSPx Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
• MSSPx Shift Register (SSPxSR) – Not directly
• MSSPx Address Register (SSPxADD)
• I
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I
SSPxCON1 and SSPxCON2 registers are readable and
writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
SSPxADD contains the slave device address when the
MSSP is configured in I
MSSP is configured in Master mode, the lower seven
bits of SSPxADD act as the Baud Rate Generator
reload value.
SSPxMSK holds the slave address mask value when
the module is configured for 7-Bit Address Masking
mode. While it is a separate register, it shares the same
SFR address as SSPxADD. It is only accessible when
the SSPM<3:0> bits are specifically set to permit
access.
Section 21.4.3.4 “7-Bit Address Masking Mode”.
In receive operations, SSPxSR and SSPxBUF
together, create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
(SSPxBUF)
accessible
2
C Slave Address Mask Register (SSPxMSK)
transmission,
Additional
REGISTERS
details
2
the
C Slave mode. When the
2
C mode operation. The
SSPxBUF
are
DS39957B-page 311
provided
is
not
2
C
in