PEF2054NV21XK Lantiq, PEF2054NV21XK Datasheet - Page 125

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Lantiq

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

The complete value for CBSR is: CBSR = 04
2) In CFI mode 0, with a frame consisting of 32 time slots, the following timing
The CBSR:CUS bits must therefore be set to “0100”, according to figure 41.
Finally, the CMD2 register bits must be set to
FC2 … 0 = 011, COC = 0, CXF = 1, CRR = 0, CBN9 … 8 = 00, i.e. CMD2 = 68
Figure 45
Timing Signals for CFI Bit Shift Example 2
The framing signal source FSC shall mark CFI time slot 4, bit 1 in downstream direction
and CFI time slot 0, bit 5 in upstream direction. The data shall be transmitted with the
rising CRCL edge and sampled with the rising CRCL edge. The FSC signal shall be
sampled with the rising DCL edge.
The following CFI register values result:
Since FSC marks the downstream bit 1, the CBSR:CDS bits must be set to “000”,
according to table 18.
If the CBSR:CDS bits are set to “000”, FSC marks the time slot TSN – 1, according to
table 18.
FSC shall mark CFI time slot 4, i.e. TSN – 1 = 4, or TSN = 4 + 1 = 5
Semiconductor Group
FSC
DCL
DD#
Required
Offset in
Downstream
Direction
Required
Offset in
Upstream
Direction
DU#
relationship between the framing signal source FSC and the data signals is required:
Bit 3
Bit 7
Bit 2
0
Time-Slot 4
Bit 6
1
Start of Internal Frame
TS4,
Bit 1
Bit 1
TS0, Bit 5
Bit 5
Time-Slot 0
Bit 0
125
H
Bit 4
Bit 7
Bit 3
Time-Slot 5
Bit 6
Bit 2
Application Hints
Bit 5
CMD2
CMD1 CSM = 1
CFI Mode 0
CMD2 CRR = 1
PEB 2055
PEF 2055
:
:
:
CXF
H
ITT08060
=
0