PEF2054NV21XK Lantiq, PEF2054NV21XK Datasheet - Page 189

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Lantiq

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

The timer is started as soon as CMDR:ST is set to 1 and stopped by writing the TIMR
register or by selecting OMDR:OMS0 = 0.
If the timer is used to generate the last look period, it can still be used for timer interrupt
generation and/or FSC multiframe generation if it is acceptable that all three applications
use the same timer value.
Command Register
CMDR
STAR
TVAL6 … 0:
Writing a logical 1 to a CMDR register bit starts the respective operation.
The signaling handler uses two command bits:
ST:
CFR:
Status Register
The status register STAR displays the current state of certain events within the EPIC.
The STAR register bits do not generate interrupts and are not modified by reading
STAR.
The following bit is indirectly used by the signaling handler:
TAC:
Semiconductor Group
bit 7
bit 7
MAC
0
Timer Value bits 6 … 0; the timer period, equal to
(1 + TVAL6 … 0) 250
adjusted within the range of 250 s up to 32 ms.
Start Timer; must be set to 1 if the last look period is defined by
TIMR:TVAL6 … 0, i.e. if TIMR:SSR = 0. Note that if TIMR:SSR = 1,
the timer need not be started.
CIFIFO Reset; setting CFR to logical 1 resets the signaling FIFO
within 2 RCL periods, i.e. all entries and the ISTA:SFI bit are cleared.
Timer Active; the timer is running if TAC is set to logical 1, the timer
is not running if TAC is set to logical 0.
Note:The timer is only necessary for signaling channels (not C/I) and
TAC
ST
when using a last look period greater or equal to 250 s.
PSS
TIG
MFTO
write
read
CFR
189
s, is programmed here. It can thus be
MFAB
MFT1
reset value:
reset value:
MFAE
MFT0
Application Hints
MFRW
MFSO
00
05
PEB 2055
H
H
PEF 2055
bit 0
bit 0
MFFR
MFFE