PEF2054NV21XK Lantiq, PEF2054NV21XK Datasheet - Page 41

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Lantiq

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

PEB 2055
PEF 2055
Operational Description
Synchronous Transfer
For two channels, all switching paths of figure 18 can also be realized using
Synchronous Transfer. The working principle is that the P specifies an input time slot
(source) and an output time slot (destination). Both source and destination time slots can
be selected independently from each other at either the PCM or CFI interfaces. In each
frame, the EPIC first transfers the serial data from the source time slot to an internal data
register from where it can be read and if required overwritten or modified by the P. This
data is then fed forward to the destination time slot.
Chapter 5.7 provides examples of such transfers.
3.4.4
Special Functions
Hardware Timer
The EPIC-1 provides a hardware timer which continuously interrupts the
P after
programmable time periods. The timer period can be selected in the range of 250 s up
to 32 ms in multiples of 250 s. Beside the interrupt generation, the timer can also be
used to determine the last look period for 6- and 8-bit signaling channels on IOM-2 and
SLD interfaces and for the generation of an FSC multiframe signal (see chapter 5.8.1).
Power and Clock Supply Supervision
The Connection Memory CM is supervised to data falsification due to clock or power
failure. If such an inappropriate clocking or power failure occurs, the P is requested to
reinitialize the device.
Semiconductor Group
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