PEF2054NV21XK Lantiq, PEF2054NV21XK Datasheet - Page 215

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Lantiq

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

5.7.1
Synchronous Transfer Data
Register A
STDA:
The STDA register buffers the data transferred over the synchronous transfer channel A.
MTDA7 to MTDA0 hold the bits 7 to 0 of the respective time slot. MTDA7 (MSB) is the
bit transmitted/received first, and MTDA0 (LSB) the bit transmitted/received last over the
serial interface.
Synchronous Transfer Data
Register B
STDB:
The STDB register buffers the data transferred over the synchronous transfer channel B.
MTDB7 to MTDB0 hold the bits 7 to 0 of the respective time slot. MTDB7 (MSB) is the
bit transmitted/received first, MTDB0 (LSB) the bit transmitted/received last over the
serial interface.
Synchronous Transfer Receive
Address Register A
SARA:
The SARA register specifies for synchronous transfer channel A from which input
interface, port, and time slot the serial data is extracted. This data can then be read from
the STDA register.
ISRA:
Semiconductor Group
Registers Used in Conjunction with the Synchronous Transfer Utility
bit 7
bit 7
MTDB7 MTDB6 MTDB5 MTDB4 MTDB3 MTDB2 MTDB1 MTDB0
bit 7
ISRA
MTDA7
Interface Select Receive for channel A; selects the PCM interface
(ISRA = 0) or the CFI (ISRA = 1) as the input interface for
synchronous channel A.
MTRA6 MTRA5 MTRA4 MTRA3 MTRA2 MTRA1 MTRA0
MTDA6
MTDA4
215
read/write reset value:
read/write reset value:
read/write reset value:
MTDA3
MTDA2
MTDA1
Application Hints
undefined
undefined
undefined
PEB 2055
PEF 2055
bit 0
bit 0
bit 0
MTDA0