PEF2054NV21XK Lantiq, PEF2054NV21XK Datasheet - Page 170

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Lantiq

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

5.4.4.2 How to Determine the Delay
In order to determine the switching delay for a certain configuration, the following rules
have to be applied with respect to the timing diagram:
Data Downstream
– At the PCM interface the incoming data (data downstream) is written to the RAM after
Note: n is an integer number.
The point of time to write the data to the RAM is RCL period 0, 4, 7 for the PCM interface
Due to internal delays, the RCL period at the beginning of time slot 2 n (for mode 0),
4 n (for mode 1), 8 n for mode 2) is not a valid write cycle.
– At the CFI interface the data, that is to be transmitted on:
is read out of the RAM as soon as time slot:
Note: n is an integer number; the time slot number can’t exceed the max. number of TS.
The point of time to read the data from the RAM is RCL period 5 and 6 for the CFI
interface.
The data is read out of the RAM in several steps in the following order:
Semiconductor Group
CFI mode 0: - even TS for DD0, odd TS for DD0,
CFI mode 1: - even TS for DD0, odd TS for DD0,
CFI mode 2: - even TS for DD0, odd TS for DD0
the beginning of:
time slot: 2 n for mode 0
time slot: 4 n for mode 1
time slot: 8 n for mode 2
TS 2 n + 4 ... 2
TS 2 n + 6 ... 2 n + 7 (CFI mode 1)
TS 2 n + 10 ... 2 n + 11 (CFI mode 2)
2 n + 1 (for mode 0)
2 n + 3 (for mode 1)
2 n + 7 (for mode 2) is transmitted
even TS for DD1, odd TS for DD1,
even TS for DD2, odd TS for DD2,
even TS for DD3, odd TS for DD3
even TS for DD1, odd TS for DD1
n + 5 (CFI mode 0)
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Application Hints
PEB 2055
PEF 2055