PEF2054NV21XK Lantiq, PEF2054NV21XK Datasheet - Page 93

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Lantiq

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

programmed PDC clock edge.
In other words, if for example the rising PFS edge has some jitter with respect to the
rising PDC edge, the falling PDC edge should be taken for the evaluation.
The high phase of the PFS pulse may be of arbitrary length, however it must be assured
that it is sampled low at least once before the next framing pulse.
The relationship between the PFS signal and the beginning of the PCM frame is given
in figure 24 and figure 25.
PCM Synchronization Mode PMOD:PSM
The PCM interface is synchronized via the PFS signal. A transition from low to high of
PFS synchronizes the PCM frame. It should be noted that the rising PFS edge does not
directly synchronize the frame, it is instead first internally sampled with the PDC clock:
If PSM is set to logical 0, the PFS signal is sampled with the falling clock edge of PDC,
if it is set to logical 1, the PFS signal is sampled with the rising clock edge of PDC.
PSM should be selected such that the PDC signal detects stable low and high levels of
the PFS signal, meeting the set-up (
PCM Bit Timing and Bit Shift POFD, POFU, PCSR
The position of the PCM frame can be shifted relative to the framing source PFS in
increments of bits by programming the PCM offset bits OFD9 … 0, OFU9 … 0 in the
POFD, POFU and PCSR. This shifting can be performed separately for up- and
downstream directions and by up to a whole frame. Additionally, the polarity of the PDC
clock edge used for transmitting and sampling the data can be selected with the URE
and DRE bits in the PCSR register.
The time slot structure on the PCM interface is synchronized with the externally applied
PFS pulse. The rising edge of PFS, after it has been sampled by the PDC signal, marks
the first bit of the PCM frame. This first bit is referenced to as the BND (Bit Number
Downstream) of the downstream and the BNU (Bit Number Upstream) of the upstream
frame.
If PCSR:URE is set to 1, data is transmitted with the rising edge of PDC, if URE is set to
0, data is transmitted with the next following falling edge of PDC.
If PCSR:DRE is set to 0, data is sampled with the falling edge of PDC, if DRE is set to
1, data is sampled with the next following rising edge of PDC.
The relationship between the PFS, PDC signals and the PCM bit stream on RxD# and
TxD# is illustrated in figure 24 and figure 25.
Semiconductor Group
T
FS
) and hold (
93
T
FH
) times with respect to the
Application Hints
PEB 2055
PEF 2055