IDT82V3355TF IDT, Integrated Device Technology Inc, IDT82V3355TF Datasheet - Page 119

• Manufacturer Part Number: IDT82V3355TF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3355TF

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

8.4
Electrical Specifications
Table 46: Output Clock Jitter Generation
IDT82V3355
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52
MHz, 311.04 MHz, 622.08 MHz output
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52
MHz, 311.04 MHz, 622.08 MHz output + Intel GD16523
+ Optical transceiver)
(Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52
MHz, 311.04 MHz, 622.08 MHz output + Intel GD16523
+ Optical transceiver)
Note:
1. CMAC E2747 TCXO is used.
N x 2.048 MHz with T0/T4 APLL
N x 1.544 MHz with T0/T4 APLL
JITTER & WANDER PERFORMANCE
44.736 MHz with T0/T4 APLL
34.368 MHz with T0/T4 APLL
N x 2.048 MHz without APLL
N x 1.544 MHz without APLL
156.25 MHz with T4 APLL
44.736 MHz without APLL
34.368 MHz without APLL
62.5 MHz with T4 APLL
125 MHz with T4 APLL
25 MHz with T4 APLL
Test Definition
STM-16
OC-12
OC-3
1
Peak to Peak
0.004 UI p-p 0.001 UI RMS
0.004 UI p-p 0.001 UI RMS
0.001 UI p-p 0.001 UI RMS
0.018 UI p-p 0.007 UI RMS
0.028 UI p-p 0.009 UI RMS
0.002 UI p-p 0.001 UI RMS
0.162 UI p-p 0.03 UI RMS
0.01 UI p-p 0.009 UI RMS
<1 ns
<1 ns
<1 ns
<1 ns
<1 ns
<1 ns
<2 ns
<1 ns
<2 ns
<1 ns
<2 ns
<1 ns
<2 ns
<1 ns
<1 ns
Typ
<200 ps
<100 ps
<200 ps
<100 ps
<200 ps
<100 ps
<200 ps
<100 ps
4.3 ps
6.9 ps
4.6 ps
16 ps
22 ps
15 ps
25 ps
RMS
Typ
119
See
See
See
See
See
See
See
See
See
See
See
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
Table 47: Output Clock Phase Noise
GR-253, G.813 Option 2
GR-253, G.813 Option 2
G.813 Option 1, G.812
G.813 Option 1, G.812
G.813 Option 1, G.812
G.813 Option 1, G.812
G.813 Option 1, G.812
G.813 Option 1
limit 0.1 UI p-p
(1 UI-6430 ps)
limit 0.5 UI p-p
(1 UI-6430 ps)
limit 0.1 UI p-p
(1 UI-6430 ps)
limit 0.1 UI p-p
(1 UI-1608 ps)
limit 0.5 UI p-p
(1 UI-1608 ps)
limit 0.1 UI p-p
(1 UI-1608 ps)
limit 0.5 UI p-p
limit 0.1 UI p-p
(1 UI-402 ps)
(1 UI-402 ps)
Note
SYNCHRONOUS ETHERNET WAN PLL
for details 1.875 MHz - 20 MHz
for details
for details 1.875 MHz - 20 MHz
for details
for details 1.875 MHz - 20 MHz
for details
for details
for details
for details
for details
for details 1.875 MHz - 20 MHz
100 Hz - 800 kHz
100 Hz - 800 kHz
12 kHz - 1.3 MHz
500 Hz - 1.3 MHz
65 kHz - 1.3 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
12 kHz - 20 MHz
250 kHz - 5 MHz
1 MHz - 20 MHz
20 Hz - 100 kHz
20 Hz - 100 kHz
10 Hz - 400 kHz
10 Hz - 400 kHz
12 kHz - 5 MHz
5 kHz - 20 MHz
10 Hz - 40 kHz
10 Hz - 40 kHz
1 kHz - 5 MHz
May 19, 2009
Test Filter