IDT82V3355TF IDT, Integrated Device Technology Inc, IDT82V3355TF Datasheet - Page 49

• Manufacturer Part Number: IDT82V3355TF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3355TF

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 35: Register List and Map (Continued)
Programming Information
IDT82V3355
Address
(Hex)
2A
2E
3A
3B
3C
3D
3E
2F
31
32
33
34
35
36
37
38
39
3F
40
IN3_CMOS_SEL_PRIORITY_CNFG -
CMOS Input Clock 3 Priority Configu-
ration *
FREQ_MON_FACTOR_CNFG - Fac-
tor of Frequency Monitor Configuration
ALL_FREQ_MON_THRESHOLD_CN
FG - Frequency Monitor Threshold for
All Input Clocks Configuration
UPPER_THRESHOLD_0_CNFG
Upper Threshold for Leaky Bucket
Configuration 0
LOWER_THRESHOLD_0_CNFG
Lower Threshold for Leaky Bucket
Configuration 0
BUCKET_SIZE_0_CNFG - Bucket
Size for Leaky Bucket Configuration 0
DECAY_RATE_0_CNFG - Decay Rate
for Leaky Bucket Configuration 0
UPPER_THRESHOLD_1_CNFG
Upper Threshold for Leaky Bucket
Configuration 1
LOWER_THRESHOLD_1_CNFG
Lower Threshold for Leaky Bucket
Configuration 1
BUCKET_SIZE_1_CNFG - Bucket
Size for Leaky Bucket Configuration 1
DECAY_RATE_1_CNFG - Decay Rate
for Leaky Bucket Configuration 1
UPPER_THRESHOLD_2_CNFG
Upper Threshold for Leaky Bucket
Configuration 2
LOWER_THRESHOLD_2_CNFG
Lower Threshold for Leaky Bucket
Configuration 2
BUCKET_SIZE_2_CNFG - Bucket
Size for Leaky Bucket Configuration 2
DECAY_RATE_2_CNFG - Decay Rate
for Leaky Bucket Configuration 2
UPPER_THRESHOLD_3_CNFG
Upper Threshold for Leaky Bucket
Configuration 3
LOWER_THRESHOLD_3_CNFG
Lower Threshold for Leaky Bucket
Configuration 3
BUCKET_SIZE_3_CNFG - Bucket
Size for Leaky Bucket Configuration 3
DECAY_RATE_3_CNFG - Decay Rate
for Leaky Bucket Configuration 3
Register Name
Input Clock Quality Monitoring Configuration & Status Registers
-
-
-
-
-
-
-
-
Bit 7
-
-
-
-
-
-
-
Bit 6
-
-
-
-
-
-
-
Bit 5
49
-
-
-
-
-
-
-
LOWER_THRESHOLD_0_DATA[7:0]
LOWER_THRESHOLD_1_DATA[7:0]
LOWER_THRESHOLD_2_DATA[7:0]
LOWER_THRESHOLD_3_DATA[7:0]
UPPER_THRESHOLD_0_DATA[7:0]
UPPER_THRESHOLD_1_DATA[7:0]
UPPER_THRESHOLD_2_DATA[7:0]
UPPER_THRESHOLD_3_DATA[7:0]
BUCKET_SIZE_0_DATA[7:0]
BUCKET_SIZE_1_DATA[7:0]
BUCKET_SIZE_2_DATA[7:0]
BUCKET_SIZE_3_DATA[7:0]
Bit 4
-
-
-
-
-
-
-
Bit 3
-
-
-
-
ALL_FREQ_HARD_THRESHOLD[3:0]
IN3_CMOS_SEL_PRIORITY[3:0]
FREQ_MON_FACTOR[3:0]
SYNCHRONOUS ETHERNET WAN PLL
Bit 2
-
-
-
-
DECAY_RATE_0_DATA
DECAY_RATE_1_DATA
DECAY_RATE_2_DATA
DECAY_RATE_3_DATA
Bit 1
[1:0]
[1:0]
[1:0]
[1:0]
Bit 0
May 19, 2009
Reference
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