IDT82V3355TF IDT, Integrated Device Technology Inc, IDT82V3355TF Datasheet - Page 22

• Manufacturer Part Number: IDT82V3355TF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3355TF

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 7: Input Clock Selection for T4 Path
3.6
mine the input clock selection, as shown in
Table 6: Input Clock Selection for T0 Path
pendently from T0 path, as determined by the T4_LOCK_T0 bit. When
the T4 DPLL locks to the T0 DPLL output, the T4 selected input clock is
a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path (refer to
Chapter 3.11.5.1 T0
the T4 path locks independently from the T0 path, the T4 DPLL input
clock selection is determined by the T4_INPUT_SEL[3:0] bits. Refer to
Table
IN2_CMOS/IN2_DIFF pairs.
Functional Description
Table 8: External Fast Selection
IDT82V3355
Control Bits - T4_INPUT_SEL[3:0]
An input clock is selected for T0 DPLL and for T4 DPLL respectively.
For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits deter-
For T4 path, the T4 DPLL may lock to a T0 DPLL output or lock inde-
External Fast selection is done between IN1_CMOS/IN1_DIFF and
Forced selection is done by setting the related registers.
FF_SRCSW (after reset)
EXT_SW
7:
1
0
other than 0000
T0 / T4 DPLL INPUT CLOCK SELECTION
Control Bits
high
low
0000
T0_INPUT_SEL[3:0]
other than 0000
Path), as determined by the T0_FOR_T4 bit. When
don’t-care
0000
IN1_CMOS_SEL_PRIORITY[3:0]
other than 0000
Control Pin & Bits
Table
don’t-care
Input Clock Selection
Input Clock Selection
External Fast selection
Automatic selection
0000
Automatic selection
Forced selection
Forced selection
6:
IN2_CMOS_SEL_PRIORITY[3:0]
22
ity monitoring and the related registers configuration.
3.6.1
Fast selection, only IN1_CMOS/IN1_DIFF and IN2_CMOS/IN2_DIFF
pairs are available for selection. Refer to
clocks quality monitoring (refer to
toring) do not affect input clock selection.
after reset (this pin determines the default value of the EXT_SW bit dur-
ing
IN1_CMOS_SEL_PRIORITY[3:0]
IN2_CMOS_SEL_PRIORITY[3:0] bits, as shown in
Table
other than 0000
Automatic selection is done based on the results of input clocks qual-
The selected input clock is attempted to be locked in T0/T4 DPLL.
The External Fast selection is supported by T0 path only. In External
The T0 input clock selection is determined by the FF_SRCSW pin
don’t-care
0000
8:
reset,
IN1_CMOS
IN2_CMOS
IN2_DIFF
IN1_DIFF
EXTERNAL FAST SELECTION (T0 ONLY)
IN1_CMOS_SEL_PRIORITY[3:0] bits
Figure 5. External Fast Selection
IN2_CMOS_SEL_PRIORITY[3:0] bits
refer
to
SYNCHRONOUS ETHERNET WAN PLL
Chapter 2
FF_SRCSW pin
Chapter 3.5 Input Clock Quality Moni-
the Selected Input Clock
Figure
bits
IN1_CMOS
IN2_CMOS
IN1_DIFF
IN2_DIFF
Pin
locked in T0 DPLL
attempted to be
5. The results of input
Description),
and
May 19, 2009
Figure 5
and
the
the