IDT82V3355TF IDT, Integrated Device Technology Inc, IDT82V3355TF Datasheet - Page 23

• Manufacturer Part Number: IDT82V3355TF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3355TF

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10: Related Bit / Register in Chapter 3.6
3.6.2
T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input
clocks quality monitoring (refer to
toring) do not affect the input clock selection.
3.6.3
validity and priority. The validity depends on the results of input clock
quality monitoring (refer to
In all the qualified input clocks, the one with the highest priority is
selected. The
INn_CMOS_SEL_PRIORITY[3:0] bits (n = 1, 2 or 3) / the
Functional Description
Note: * The setting in the 27, 28 and 2A registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
IDT82V3355
In Forced selection, the selected input clock is set by the
In Automatic selection, the input clock selection is determined by its
FORCED SELECTION
AUTOMATIC SELECTION
INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3)
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
priority is
T0_INPUT_SEL[3:0]
T4_INPUT_SEL[3:0]
Chapter 3.5 Input Clock Quality
T4_LOCK_T0
T0_FOR_T4
T4_T0_SEL
EXT_SW
configured by
Bit
Chapter 3.5 Input Clock Quality Moni-
the corresponding
Monitoring).
23
Table 9: ‘n’ Assigned to the Input Clock
INn_DIFF_SEL_PRIORITY[3:0] bits (n = 1 or 2). If more than one quali-
fied input clock is available and has the same priority, the input clock
with the smallest ‘n’ is selected. See
input
IN1_IN2_CMOS_SEL_PRIORITY_CNFG,
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
IN3_CMOS_SEL_PRIORITY_CNFG
clock.
T4_T0_REG_SEL_CNFG
MON_SW_PBO_CNFG
T0_INPUT_SEL_CNFG
T4_INPUT_SEL_CNFG
Input Clock
IN1_CMOS
IN2_CMOS
IN3_CMOS
IN1_DIFF
IN2_DIFF
Register
SYNCHRONOUS ETHERNET WAN PLL
Table 9
‘n’ Assigned to the Input Clock
for the ‘n’ assigned to the
1
2
3
4
5
Address (Hex)
May 19, 2009
27 *, 2A *
28 *
0B
50
51
07