LC5512MB-75F256I Lattice, LC5512MB-75F256I Datasheet - Page 16

• Manufacturer Part Number: LC5512MB-75F256I
• Description: LATLC5512MB-75F256I 512MC CPLD 150K Gate
• Manufacturer: Lattice

Lattice Semiconductor
Figure 15. PLL Block Diagram
Figure 16. Connection of Optional PLL Inputs and Outputs
In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N
and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The
K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and
feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintain-
ing a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay feature that allows the out-
put clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more
information on the PLL, please refer to Lattice technical note number TN1003, Lattice sysCLOCK PLL Usage
Guidelines.
PLL_FBK
PLL_RST
CLK_IN
From Macrocell
From Macrocell
From Macrocell
*See pinout table for details
PLL_LOCK
Input Clock
CLK_OUT
(M) Divider
PLL_FBK
PLL_RST
To GRP
To GRP
To GRP
To GRP
Programable
(N) Divider
Feedback
Delay
Loop
Detector
Phase
VCO
and
16
Post-scalar
ispXPLD 5000MX Family Data Sheet
Secondary
(V) Divider
(K) Divider
Clock
CLK_OUT
PLL_LOCK
SEC_OUT
I/O Pin*
I/O Pin*
I/O Pin*
Clock Net
Clock Net