LC5512MB-75F256I Lattice, LC5512MB-75F256I Datasheet - Page 74

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LC5512MB-75F256I

Manufacturer Part Number
LC5512MB-75F256I
Description
LATLC5512MB-75F256I 512MC CPLD 150K Gate
Manufacturer
Lattice
Datasheet

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Lattice Semiconductor
ispXPLD 5768MX Logic Signal Connections (Continued)
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs.
sysIO Bank LVDS Pair
0
0
126N
126P
Primary Macrocell/
Function
S26
S24
Macrocell 1
S13
S12
Alternate Outputs
74
Macrocell 2
-
-
ispXPLD 5000MX Family Data Sheet
Alternate
Inputs
S27
S25
Ball Number
256 fpBGA
Ball Number
484 fpBGA
C4
D5

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