LC5512MB-75F256I Lattice, LC5512MB-75F256I Datasheet - Page 49

• Manufacturer Part Number: LC5512MB-75F256I
• Description: LATLC5512MB-75F256I 512MC CPLD 150K Gate
• Manufacturer: Lattice

Lattice Semiconductor
Signal Descriptions
TMS
TCK
TDI
TDO
TOE
GOE0, GOE1
RESET
yzz
GND
NC
V
V
V
GCLK0, GCLK1, GCLK2, GCLK3
CLK_OUT0, CLK_OUT1
PLL_RST0, PLL_RST1
PLL_FBK0, PLL_FBK1
GNDP
V
V
DATA
CSB
CFG0
PROGRAMB
CCLK
READ
INITB
DONE
1. These inputs should not toggle during power up for proper power-up configuration.
CC
CCO0,
REF0,
CCP
CCJ
x
1
1
V
V
REF1,
CCO1,
Signal Names
V
V
REF2,
CCO2,
V
V
REF3
CCO3
Input – This pin is the Test Mode Select input, which is used to control the IEEE 1149.1
state machine.
Input – This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state
machine.
Input – This pin is the IEEE 1149.1 Test Data in pin, used to load data.
Output – This pin is the IEEE 1149.1 Test Data out pin used to shift data out.
Input – Test Output Enable pin. TOE tristates all I/O pins when driven low.
Input – Global output enable inputs.
Input – This pin resets all the registers in the device. The global polarity for this pin is
selectable on a global basis. The default is active low. An external pull-down is required
when polarity is set to active high.
Input/Output – These are the general purpose I/O used by the logic array.
reference (alpha) and z is the macrocell reference (numeric)
y: A-X (768 macrocells)
y: A-P (512 macrocells)
y: A-H (256 macrocells)
z: 0-31
GND – Ground
No connect
V
V
Input – This pin defines the reference voltage for I/O banks 0, 1, 2, and 3.
Input – Global clock/clock enable inputs (see Figure 14 for differential pairing).
Output – Optional clock output from PLL 0 and 1.
Input – Optional input resets the M divider in PLL 0 and 1.
Input – Optional feedback input for PLL 0 and 1.
GND – Ground for PLLs.
V
V
I/O – sysCONFIG data pins, bit
Input – sysCONFIG interface chip select. Drive low to select sysCONFIG interface.
Input – Defines SRAM configuration mode. Low: sysCONFIG port, high: E
IEEE 1149.1 TAP.
Input – Controls the programming of SRAM. Hold high for normal operation. Toggle low
to reload SRAM from E
Input – Clock for sysCONFIG interface. Reads and writes occur on the rising edge of
the clock.
Input – Drive high to perform reads from the sysCONFIG interface.
I/O – Indicates status of configuration. Can be driven low to inhibit configuration.
Output (open drain) – Indicates status of configuration.
CC
CC
CC
CC
– The power supply pins for core logic.
– The power supply pins for I/O banks 0, 1, 2, and 3.
– The power supply pin for PLLs.
– The power supply for the IEEE 1149.1 interface.
49
2
memory.
x
.
ispXPLD 5000MX Family Data Sheet
Descriptions
y
2
CMOS or
is the MFB