LC5512MB-75F256I Lattice, LC5512MB-75F256I Datasheet - Page 55

• Manufacturer Part Number: LC5512MB-75F256I
• Description: LATLC5512MB-75F256I 512MC CPLD 150K Gate
• Manufacturer: Lattice

Lattice Semiconductor
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs
ispXPLD 5256MX Logic Signal Connections (Continued)
sysIO Bank LVDS Pair
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
51N
51P
52N
52P
53N
53P
54N
54P
55N
55P
56N
56P
57N
57P
58N
58P
59N
59P
60N
60P
-
-
-
-
-
Primary Macrocell/
GND (Bank 0)
GND (Bank 0)
G16/VREF0
Function
VCCO0
VCCO0
GND
G30
G28
G26
G24
G22
G21
G20
G18
G14
G12
G10
G8
G6
G5
G4
G2
G0
F2
F0
Macrocell 1
G31
G30
G29
G28
G27
G26
G25
G24
G23
G22
G21
G20
G19
G18
G3
G2
G1
G0
E1
E0
55
Alternate Outputs
-
-
-
-
-
Macrocell 2
ispXPLD 5000MX Family Data Sheet
H31
H30
H29
H28
H27
H26
H25
H24
H23
H22
H21
H20
H19
H18
H3
H2
H1
H0
F1
F0
-
-
-
-
-
Alternate Input
G31
G29
G27
G25
G23
G19
G17
G15
G13
G11
G9
G7
G3
G1
F3
F1
-
-
-
-
-
-
-
-
-
GND (Bank 0)
GND (Bank 0)
Ball Number
256 fpBGA
VCCO0
VCCO0
NC
B8
C8
B7
A7
D7
C7
B6
E7
E6
A6
A5
A4
B5
A3
B4
B3
C5
C6
D5
D6