LC5512MB-75F256I Lattice, LC5512MB-75F256I Datasheet - Page 30

• Manufacturer Part Number: LC5512MB-75F256I
• Description: LATLC5512MB-75F256I 512MC CPLD 150K Gate
• Manufacturer: Lattice

ispXPLD 5000MX Family External Switching Characteristics (Continued)
Lattice Semiconductor
f
f
t
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate timing for other standards.
2. Measured using standard switching circuit, global routing loading of 1, worst case PTSA loading and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
5. CAM, FIFO, RAM f
MAX
MAX
PWR_ON
Parameter
(RAM)
(FIFO)
5
5
Clock Frequency to RAM in:
Single Port Mode
Dual Port Mode
Pseudo Dual Port Mode
Clock Frequency to FIFO
Power-on Time
MAX
specification used shared PT Clk.
Description
Over Recommended Operating Conditions
Min.
—
—
—
—
—
-4
Max.
155
155
180
225
200
30
Min.
—
—
—
—
—
-45
Max.
155
155
180
220
200
ispXPLD 5000MX Family Data Sheet
Min.
—
—
—
—
—
-5
Max.
155
155
160
210
200
Min.
—
—
—
—
—
-52
Max.
155
155
160
210
200
Min.
—
—
—
—
—
-75
Max.
106
132
200
93
93
Timing v.1.8
1, 2, 3
Units
MHz
MHz
MHz
MHz
µs