EP3C40F780C6N Altera, EP3C40F780C6N Datasheet - Page 196

• Manufacturer Part Number: EP3C40F780C6N
• Description: IC CYCLONE III FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F780C6N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 535
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 535
• Frequency (max): 500MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2502

9–36
Cyclone III Device Handbook, Volume 1
To ensure DCLK and DATA[0] are not left floating at the end of configuration, the
MAX II device must drive them either high or low, whichever is convenient on your
board. The DATA[0] pin is available as a user I/O pin after configuration. In the PS
scheme, the DATA[0] pin is tri-stated by default in user mode and must be driven by
the external host device. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device and Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified system frequency
to ensure correct configuration
period exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If a configuration error occurs during configuration and the Auto-restart
configuration after error option is turned on, the Cyclone III device family releases
nSTATUS after a reset time-out period (a maximum of 230 μs). After nSTATUS is
released and pulled high by a pull-up resistor, the external host device tries to
reconfigure the target device without needing to pulse nCONFIG low. If this option is
turned off, the external host device must generate a low-to-high transition (with a low
pulse of at least 500 ns) on nCONFIG to restart the configuration process.
The external host device can also monitor the CONF_DONE and INIT_DONE pins to
ensure successful configuration. The CONF_DONE pin must be monitored by the
external device to detect errors and to determine when the programming is complete.
If all configuration data is sent, but CONF_DONE or INIT_DONE has not gone high, the
external device must reconfigure the target device.
Figure 9–15
This circuit is similar to the PS configuration circuit for a single device, except that the
Cyclone III device family is cascaded for multi-device configuration.
Figure 9–15. Multi-Device PS Configuration Using an External Host
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
chain. V
refer to
equation outlined in
(MAX II Device or
Microprocessor)
External Host
Figure
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
ADDR
Table 9–7 on page
CC
must be high enough to meet the V
Memory
shows how to configure multiple devices using an external host device.
9–15:
DATA[0]
“Configuration and JTAG Pin I/O Requirements” on page
V CCIO (1) V CCIO (1)
10 k
9–11. Connect the MSEL pins directly to V
10 k
GND
CCIO
(Figure 9–19 on page
supply voltage of the I/O bank in which the nCE pin resides.
Buffers (5)
Cyclone III Device Family 1
CONF_DONE
DATA[0] (5)
nCONFIG
DCLK (5)
nCE
IH
nSTATUS
specification of the I/O on the device and the external host.
MSEL[3..0]
nCEO
(4)
9–42). No maximum DCLK
CCA
V CCIO (2)
or ground.
© December 2009 Altera Corporation
10 k
9–7.
Cyclone III Device Family 2
CONF_DONE
nCE
nCONFIG
DATA[0] (5)
DCLK (5)
nSTATUS
MSEL[3..0]
Configuration Features
nCEO
N.C. (3)
(4)