EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 508

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Notes to
(1)
(2)
Output t
t
t
f
(LVDS,LVPECL, HyperTransport
technology)
f
DUTY
LOCK
HSCLK
HSCLK
Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 3 of 3)
Table 5–8. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 3)
When J = 4, 7, 8, and 10, the SERDES block is used.
When J = 2 or J = 1, the SERDES is bypassed.
Symbol
(Clock frequency)
= f
FALL
Table
HSDR
Symbol
/ W
5–7:
LVDS
HyperTransport
technology
LVPECL
PCML
LVDS (J = 2 through
10)
LVDS (J =1) and
LVPECL, PCML,
HyperTransport
technology
All
Conditions
W = 4 to 30 (Serdes used)
W = 2 (Serdes bypass)
W = 2 (Serdes used)
W = 1 (Serdes bypass)
W = 1 (Serdes used)
47.5
Min
110
105
80
90
45
-5 Speed Grade
Conditions
Typ
110
170
130
140
50
50
Max
52.5
120
200
160
175
100
55
47.5
Min
110
105
80
90
45
-6 Speed Grade
Min
150
100
300
50
10
-6 Speed Grade
110
170
130
140
Typ
50
50
Typ
Notes
Max
52.5
120
200
160
175
100
55
(1),
Max
156
231
312
311
624
47.5
Min
110
100
110
(2)
80
45
-7 Speed Grade
Min
150
100
300
10
50
-7 Speed Grade
110
170
135
145
Typ
50
50
Typ
Max
52.5
120
200
160
175
100
55
115.5
Max
231
231
270
462
47.5
Min
110
100
110
80
45
-8 Speed Grade
Min
150
100
300
10
50
-8 Speed Grade
Typ
110
170
135
145
50
50
Typ
Max
52.5
120
200
160
175
100
55
115.5 MHz
Max
231
231
270
462
Unit
ps
ps
ps
ps
%
%
MHz
MHz
MHz
MHz
Unit
s