EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 696

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

TriMatrix Memory
10–12
Stratix Device Handbook, Volume 2
always output a don’t care value.
through behavior of the mixed-port mode. You can use the altsyncram
megafunction to set the output behavior during mixed-port read-during-
write mode.
Figure 10–7. Mixed-Port Feed-Through Behavior (OLD_DATA)
Note to
(1)
Figure 10–8. Mixed-Port Feed-Through Behavior (DONT_CARE)
Note to
(1)
Memory Megafunctions
To convert RAM and ROM originally targeting the APEX II or APEX 20K
architecture to Stratix or Stratix GX memory, specify Stratix or Stratix GX
as the target family in the MegaWizard Plug-In Manager. The software
Figures 10–7
the outputs are not registered.
Figures 10–7
the outputs are not registered.
Figure
Figure
10–7:
10–8:
address A and
address A and
and
and
address B
address B
data_out
data_out
10–8
10–8
data_in
data_in
inclock
inclock
Port A
Port A
Port B
Port B
Port A
Port A
Port B
Port B
wren
wren
wren
wren
assume that the address stays constant throughout and that
assume that the address stays constant throughout and that
A
A
Unknown
Old
Figures 10–7
Address Q
Address Q
A
B
B
and
10–8
B
B
Altera Corporation
show the feed-
Note (1)
Note (1)
July 2005