EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 552

IC STRATIX FPGA 40K LE 956-BGA

EP1S40B956C5

Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40B956C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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DSP Block Overview
DSP Block
Overview
6–2
Stratix Device Handbook, Volume 2
Each Stratix and Stratix GX device has two columns of DSP blocks that
efficiently implement multiplication, multiply accumulate (MAC), and
filtering functions.
surrounding LAB rows. You can configure each DSP block to support:
Figure 6–1. DSP Blocks Arranged in Columns
The multipliers can then feed an adder or an accumulator block,
depending on the DSP block operational mode. Additionally, you can use
the DSP block input registers as shift registers to implement applications
such as FIR filters efficiently. The number of DSP blocks per column
Eight 9
Four 18
One 36
8 LAB
Rows
36 bit multiplier
9 bit multipliers
18 bit multipliers
Figure 6–1
shows one of the columns with
DSP Block
DSP Block
Column
Altera Corporation
July 2005

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