EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 634

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Discrete Cosine Transform (DCT)
7–56
Stratix Device Handbook, Volume 2
All of the additions in stages 1, 2 and 3 of
symmetric add and subtract pairs. The entire first stage is simply four
such pairs in a very typical cross-over pattern. This pattern is repeated in
stages 2 and 3. Multiplication operations are confined to stage 4 in the
algorithm. This implementation is shown in more detail in the next
section.
DCT Implementation
In taking advantage of the separable transform property of the DCT, the
implementation can be divided into separate stages; row processing and
column processing. However, some data restructuring is necessary
before applying the column processing stage to the results from the row
processing stage. The data buffering stage must transpose the data first.
Figure 7–34
Figure 7–34. Three Separate Stages in Implementing the 2-D DCT
Because the row processing and column processing blocks share the same
1-D 8-point DCT algorithm, the hardware implementation shows this
block as being shared. The DCT algorithm requires a serial-to-parallel
conversion block at the input because it works on blocks of eight data
processing
C
C
x
Row
=
=
cos
shows the different stages.
1
0
0
0
0
0
0
0
----- -
16
x
C
0
0
0
0
0
0
0
4
C
C
0
0
0
0
0
0
6
2
–
C
C
0
0
0
0
0
0
6
2
Transpose
C
C
C
C
0
0
0
0
matrix
7
5
3
1
–
–
–
C
C
C
C
0
0
0
0
3
5
1
7
–
C
C
C
0
0
0
0
C
Figure 7–32
3
7
5
1
–
–
C
C
C
C
0
0
0
0
3
7
1
5
appear in
Altera Corporation
September 2004
processing
Column