EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 816

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Using Enhanced Configuration Devices
Figure 12–21. Specifying Block Addresses for an Application Configuration
12–38
Stratix Device Handbook, Volume 2
A sample memory map output file for the preceding example is shown
below. Note that the allocated memory for page 1 is between
0x00070000 and 0x000BFFFF, while the actual region used by the
current application configuration bitstream is between 0x0007B144 and
0x000BFFFF. The configuration data is top justified within the allocated
SOF data region. Similarly, the allocated memory for page 2 is between
0x000D0000 and 0x0012FFFF, while the actual region used by the
application configuration is between 0x000EB13E and 0x0012FFF9.
Also note that the HEX data stored in the main data area uses absolute
addressing. If relative addressing were to be used, the main data contents
would be justified with the top (higher address locations) of the memory.
The initial POF can be converted to an Intel Hexadecimal format file
(*.HEXOUT) using the Quartus II CPF utility. See
BOTTOM BOOT
OPTION BITS
PAGE 0
PAGE 1
PAGE 2
TOP BOOT/MAIN
Block
0x00000000
0x00010000
0x00010040
0x0007B144
0x000EB13E
0x001F0000
Start Address
Figure
0x000001FF
0x0001003F
0x00054EFA
0x000BFFFF
0x0012FFF9
0x001F01FF
Altera Corporation
End Address
12–22.
September 2004