MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 141

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The following eight user floating-point arithmetic exceptions are listed in order of priority.
INEX1 exception is the condition that exists when a packed decimal operand cannot be con-
verted exactly to the extended-precision format in the current rounding mode. Since the
MC68060 does not directly support packed decimal real operands, the processor never sets
INEX1 bit in the FPSR EXC byte, but provides it as a latch so that the M68060SP (emulation
software) can report the exception.
The processor takes a floating-point arithmetic exception in one of two situations. The first
situation occurs when the user program enables an arithmetic exception by setting a bit in
the FPCR ENABLE byte and the corresponding bit in the FPSR EXC byte matches the bit
in the FPCR ENABLE byte as a result of program execution. This is referred to as a
maskable exception condition since it is possible to prevent an exception from occurring. All
exceptions except the OVFL and UNFL are maskable. For the SNAN, OPERR, DZ, and
INEX enabled exception cases, some assistance from the M68060SP is required to provide
MC68881-compatible operation. Therefore, the M68060SP supervisor exception handler is
executed before handing control over to the user-supplied exception handler.
Note that a user write operation to the FPSR, which sets a bit in the EXC byte, does not
cause an exception to be taken, regardless of the value in the ENABLE byte. When a user
writes to the ENABLE byte that enables a class of floating-point exceptions, a previously
generated floating-point exception does not cause an exception to be taken, regardless of
the value in the FPSR EXC byte. The user can clear a bit in the FPCR ENABLE byte, dis-
abling each corresponding exception.
The second situation that will cause the processor to take a floating-point arithmetic excep-
tion occurs when the processor encounters an OVFL or UNFL condition. These exceptional
conditions are non-maskable, requiring the M68060SP to correct a defaulting result gener-
ated by the MC68060 that is different from the result generated by an MC68881/MC68882
executing the same code. After correcting the result, the M68060SP exception handler
hands control over to a user-defined exception handler if the exception has been enabled in
the FPCR ENABLE byte or returns to the main program flow if the exception is disabled.
As outlined in 6.5.1 Unimplemented Floating-Point Instructions to 6.5.3 Unimple-
mented Effective Address Exception, there are certain conditions such that the
M68060SP reports floating-point arithmetic exceptions as part of handling an unimple-
mented floating-point instruction, unimplemented effective address, or unsupported data
MOTOROLA
• Branch/Set on Unordered (BSUN)
• Signaling Not-A-Number (SNAN)
• Operand Error (OPERR)
• Overflow (OVFL)
• Underflow (UNFL)
• Divide-by-Zero (DZ)
• Inexact 2 (INEX2)
• Inexact 1 (INEX1)
M68060 USER’S MANUAL
Floating-Point Unit
6-23