MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 44

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Introduction
1-20
ROXL, ROXR Destination Rotated with X by count ˘ Destination
ROL, ROR
ORI to SR
PFLUSH 7
Opcode
TRAPcc
RESET
TRAPV
SWAP
PACK
SBCD
STOP
SUBA
SUBQ
SUBX
UNPK
TRAP
UNLK
PLPA
SUBI
RTD
RTR
SUB
PEA
RTE
RTS
TAS
TST
Scc
If supervisor state
else TRAP
Source (Unpacked BCD) + adjustment ˘
SP – 4 ˘ SP; <ea> ˘ (SP)
If supervisor state
else TRAP
If supervisor state
else TRAP
If supervisor state
else TRAP
Destination Rotated by count ˘ Destination
(SP) ˘ PC; SP + 4 + d n ˘ SP
If supervisor state
else TRAP
(SP) ˘ CCR; SP + 2 ˘ SP;
(SP) ˘ PC; SP + 4 ˘ SP
(SP) ˘ PC; SP + 4 ˘ SP
Destination
If condition true
else 0s ˘ Destination
If supervisor state
else TRAP
Destination – Source ˘ Destination
Destination – Source ˘ Destination
Destination – Immediate Data ˘ Destination
Destination – Immediate Data ˘ Destination
Destination – Source – X ˘ Destination
Register 31–16 ¯ ˘ Register 15–0
Destination Tested ˘ Condition Codes;
SSP – 2 ˘ SSP; Format
SSP – 4 ˘ SSP; PC ˘ (SSP); SSP – 2 ˘ SSP;
SR ˘ (SSP); Vector Address ˘ PC
If cc
If V
Destination Tested ˘ Condition Codes
An ˘ SP; (SP) ˘ An; SP + 4 ˘ SP
Source (Packed BCD) + adjustment ˘ Destination (Unpacked
BCD)
then logical address translate to physical
address ˘ An
then Source V SR ˘ SR
Destination (Packed BCD)
then invalidate instruction and data ATC entries
for destination address
then Assert RSTO Line
then (SP) ˘ SR; SP + 2 ˘ SP; (SP) ˘ PC;
SP + 4 ˘ SP; restore state and deallocate
stack according to (SP)
then 1s ˘ Destination
then Immediate Data ˘ SR; STOP
1 ˘ bit 7 of Destination
then TRAP
then TRAP
Table 1-3. Instruction Set Summary (Continued)
10
– Source
10
– X ˘ Destination
Offset ˘ (SSP);
Operation
M68060 USER’S MANUAL
ORI #<data>,SR
PACK –(Ax),–(Ay),#(adjustment)
PACK Dx,Dy,#(adjustment)
PEA <ea>
PFLUSH (An)
PFLUSHN (An)
PFLUSHA
PFLUSHAN
PLPAR (An)
PLPAW (An)
RESET
ROd Rx,Dy1
ROXd Dx,Dy
ROXd #<data>,Dy
ROXd <ea>
RTD #(d n )
RTE
RTR
RTS
SBCD Dx,Dy
SBCD –(Ax),–(Ay)
Scc <ea>
STOP #<data>
SUB <ea>,Dn
SUB Dn,<ea>
SUBA <ea>,An
SUBI #<data>,<ea>
SUBQ #<data>,<ea>
SUBX Dx,Dy
SUBX –(Ax),–(Ay)
SWAP Dn
TAS <ea>
TRAP #<vector>
TRAPcc
TRAPcc.W #<data>
TRAPcc.L #<data>
TRAPV
TST <ea>
UNLK An
UNPACK –(Ax),–(Ay),#(adjustment)
UNPACK Dx,Dy,#(adjustment)
1
1
Syntax
1
MOTOROLA