MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 379

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MC68060 Software Package
M68060FPSP SNAN and OPERR exception handlers, _fpsp_snan and _fpsp_operr, will be
provided for SNAN and OPERR enabled exceptions for the following reasons:
A simple pseudo-code diagram for the SNAN and OPERR handlers is provided in the code
sequence shown in Figure C-8.
C.3.2.3.3 Inexact Exception. Opclass zero and two exception instructions taking the inex-
act exception cause pre-instruction exceptions, and opclass three instructions cause post-
instruction inexact exceptions. The processor takes exception vector number forty-nine for
the inexact exception. The FSAVE frame for the exception is valid and contains the source
operand converted to extended precision.
The inexact exception is a maskable exception on the MC68060 for the trap-disabled case.
The floating-point hardware produces the correct result when the inexact exception enable
C-18
• For opclass two pre-instruction exceptions using a single or double source format with
• For opclass three post-instruction exceptions, the processor does not store the default
an infinity, denorm, NAN, or zero source operand, the processor does not create the
correct extended-precision value for the FSAVE frame. The MC68060FPSP handlers
convert the value in the FSAVE frame to extended-precision format before passing con-
trol to the user enabled SNAN or OPERR exception handlers (_real_{snan,operr}). No
parameters are passed to the user enabled SNAN or OPERR exception handlers from
the M68060FPSP package since the package provides the illusion that it never existed.
result to the destination memory or integer data register before taking the enabled ex-
ception. The MC68881/882 stored the default result in this scenario. Therefore, to main-
tain compatibility, the M68060FPSP SNAN and OPERR exception handlers calculate
and store the default result before passing control to the user enabled SNAN and OP-
ERR exception handlers (_real_{snan,operr}). No parameters are passed to the user
SNAN or OPERR exception handlers since the M68060FPSP provides the illusion that
it never existed.
_fpsp_{snan,operr}() {
if ((opclass == 0) || (opclass == 2)) {
}
else {/* opclass 3 */
Figure C-8. SNAN/OPERR Exception Handler Pseudo-Code
/*
fix_FSAVE_op();
bra.l _real_{snan,operr}();
/*
save_default_result();
bra.l _real_{snan,operr}();
* if src operand is a sgl or dbl
* zero,NAN,denorm, or infinity,
* fix operand in FSAVE frame.
*/
* save default result to memory
* or integer register file.
*/
M68060 USER’S MANUAL
MOTOROLA