MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 369

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MC68060 Software Package
Assuming that the system integrator elects to use the _isp_cas() and _isp_cas2() entry
points for instruction emulation, three routines are made available to the access error excep-
tion handler to provide more options when a bus error (TEA) is encountered when in these
critical routines:
As long as the _real_lock_page() routine operates properly, only physical bus errors caused
by the PLPA or MOVES instructions can occur within the critical code sequence. It is the
access error handler’s responsibility to determine whether or not it is appropriate to restart
the locked sequence or to terminate the CAS or CAS2 emulation. More than likely, at the
time of the bus error, all maskable interrupts have been masked. It is the responsibility of
the access error handler to re-enable the interrupts if desired.
For the recoverable bus error cases, the stacked PC of the access error frame can be
replaced with the _isp_cas_restart() address once the cause of the bus error has been
removed. Code execution continues at the _isp_cas_restart() entry point, when the RTE of
the access error handler is executed.
For the non-recoverable bus error case, the stacked PC must be replaced with the
_isp_cas_terminate() address to ensure that the original CAS or CAS2 emulation stack
frame is removed from the system stack, and system is placed in the same state just before
the CAS or CAS2 emulation was attempted. Also, the Fault Address FSLW must be copied
to the appropriate registers prior to executing the RTE of the access error handler. After the
RTE instruction is executed, code execution resumes at the _isp_cas_terminate() entry
point. When the access error handler is re-entered, the stacked PC contains the address of
the CAS or CAS2 instruction, the Fault Address contains the passed Fault Address from the
previous access error handling, and the FSLW contains the passed FSLW from the previous
access error handling. Figure C-4 outlines the call-outs and entry-points associated with the
CAS and CAS2 emulation.
C-8
1. _isp_cas_inrange(): Accepts an instruction address as an input argument and returns
2. _isp_cas_restart(): If an access error handler encounters a recoverable physical bus
3. _isp_cas_terminate(): If an access error handler encounters a non-recoverable phys-
a failing or passing value corresponding to whether the address is within the
_isp_cas() or _isp_cas2() code region. This function can be used within a system’s ac-
cess error handler to determine if a PLPA or MOVES instruction has incurred a bus
error (TEA asserted) within the _isp_cas() or _isp_cas2() code region.
error (TEA asserted) and the _isp_cas_inrange() routine returns an “in-range” value,
then the operand read/write sequence will be restarted through this entry point. Note
that by design of the MC68060, any exception occurring while LOCK is asserted au-
tomatically negates it.
ical bus error (TEA asserted) and the _isp_cas_inrange() routine returns an “in-range”
value, it can re-enter the package through this entry point. The package creates a new
access error frame.
M68060 USER’S MANUAL
MOTOROLA