MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 45

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

1.10 NOTATIONAL CONVENTIONS
Table 1-4 lists the notation conventions used throughout this manual.
MOTOROLA
NOTES:
If <condition>
else <operations>
then <operations>
Opcode
<operand>tested
1.Where d is direction, left or right.
2.Emulation support only, not supported in hardware.
3.Where r is rounding precision, single or double precision.
4.List refers to register.
5.List refers to control registers only.
6.MOVE16 (ax)+,(ay)+ is functionally the same as MOVE16 (ax),(ay)+ when ax = ay. The address register is
only incremented once, and the line is copied over itself rather than to the next line.
7.Not available for the MC68EC060.
8.Emulation support for misaligned operands.
9.Emulation support for FMCVEM with dynamic register list.
sign-extended
<operand> 10
Dx, Dy
Ax, Ay
Dh, Dl
Dr, Dq
TRAP
STOP
<op>
MRn
BR
An
Dc
Dn
Du
¯ ˘
+
–
~
+
•
˘
Arithmetic addition or postincrement indicator.
Arithmetic subtraction or predecrement indicator.
Arithmetic multiplication.
Arithmetic division or conjunction symbol.
Invert; operand is logically complemented.
Logical AND
Logical OR
Logical exclusive OR
Source operand is moved to destination operand.
Two operands are exchanged.
Any double-operand operation.
Operand is compared to zero and the condition codes are set appropriately.
All bits of the upper portion are made equal to the high-order bit of the lower portion.
Equivalent to Format
(SSP); SSP – 2 ˘ SSP; (Vector) ˘ PC
Enter the stopped state, waiting for interrupts.
The operand is BCD; operations are performed in decimal.
Test the condition. If true, the operations after “then” are performed. If the condition is false and
the optional “else” clause is present, the operations after “else” are performed. If the condition is
false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction de-
scription as an example.
Any Address Register n (example: A3 is address register 3)
Source and destination address registers, respectively.
Base Register—An, PC, or suppressed.
Data register D7–D0, used during compare.
Data registers high- or low-order 32 bits of product.
Any Data Register n (example: D5 is data register 5)
Data register’s remainder or quotient of divide.
Data register D7–D0, used during update.
Source and destination data registers, respectively.
Any Memory Register n.
Table 1-3. Instruction Set Summary (Continued)
Table 1-4. Notational Conventions
Single- And Double-Operand Operations
Operation
M68060 USER’S MANUAL
Register Specification
Offset Word ˘ (SSP); SSP – 2 ˘ SSP; PC ˘ (SSP); SSP – 4 ˘ SSP; SR ˘
Other Operations
Syntax
Introduction
1-21