DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 19

• Manufacturer Part Number: DP83953VUL
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83953VUL

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 870mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83953VUL

4.0 Functional Description
Methods of RIC2A Cascading
In order to build multi-RIC2A repeaters, PORT N and
PORT M identification must be performed across all the
RIC2As in the system. Inside each RIC2A, the PSMs are
arranged in a logical arbitration chain where port 1 is the
highest and port 13 the lowest. The top of the chain, the
input to port 1 is accessible to the user via the RIC2A's
ACKI input pin. The output from the bottom of the chain
becomes the ACKO output pin. In a single RIC2A system
PORT N is defined as the highest port in the arbitration
chain with receive or collision activity. Port N identification
is performed when the repeater is in the IDLE state. PORT
M is defined as the highest port in the chain with a collision
when the repeater leaves the TRANSMIT COLLISION
state. In order for the arbitration chain to function, all that
needs to be done is to tie the ACKI signal to a logic high
state. In multi-RIC2A systems there are two methods to
propagate the arbitration chain between RIC2As:
The first and most straight forward is to extend the arbitra-
tion chain by daisy chaining the ACKI ACKO signals
between RIC2As. In this approach one RIC2A is placed at
the top of the chain (its ACKI input is tied high), then the
ACKO signal from this RIC2A is sent to the ACKI input of
the next RIC2A and so on. This arrangement is simple to
implement but it places some topological restrictions upon
the repeater system. In particular, if the repeater is con-
structed using a backplane with removable printed circuit
boards. (These boards contain the RIC2As and their asso-
ciated components.) If one of the boards is removed then
the ACKI ACKO chain will be broken and the repeater will
not operate correctly.
The second method of PORT N or M identification avoids
this problem. This second technique relies on an external
parallel arbiter which monitors all of the RIC2As' ACKO sig-
nals and responds to the RIC2A with the highest priority. In
this scheme each RIC2A is assigned with a priority level.
One method of doing this is to assign a priority number
which reflects the position of a RIC2A board on the
repeater backplane, i.e., its slot number. When a RIC2A
experiences receive activity and the repeater system is in
the IDLE state, the RIC2A board will assert ACKO. Exter-
nal arbitration logic drives the identification number onto an
arbitration bus and the RIC2A containing PORT N will be
identified. An identical procedure is used in the TRANSMIT
COLLISION state to identify PORT M. Parallel arbitration is
not subject to the problems caused by missing boards, i.e.,
empty slots in the backplane. The logic associated with
asserting this arbitration vector in the various packet repeti-
tion scenarios could be implemented in PAL® or GAL®
type devices.
Both of the above methods employ the same signals:
ACKI, ACKO and ACTN to perform PORT N or M arbitra-
tion.
The Inter-RIC bus allows multi-RIC2A operations to be per-
formed in exactly the same manner as if there is only a sin-
gle RIC2A in the system. The simplest way to describe the
operation of Inter-RIC bus is to see how it is used in a num-
ber of common packet repetition scenarios.
(Continued)
19
4.4 Examples Of Packet Repetition Scenarios
The operation of RIC2A is described by the following exam-
ples of packet repetition scenarios.
Data Repetition Overview
When a packet is received at one port, the RIC2A checks
the source, and destination addresses of the packet. The
port configuration causes either a pseudo random bit
sequence, or the received packet to be transmitted to differ-
ent ports.
If there is a destination address mismatch (secure mode),
then the RIC2A will generate a random pattern from the
first bit of the data field to that port. The data remains intact
on the Inter-RIC bus so other cascaded repeaters could
compare the destination address with their local CAMs.
On a valid source address mismatch (secure mode),
RIC2A shall switch to random pattern both on the local
transmitting ports and the Inter-RIC bus.
Collision Scenarios Overview
The RIC2A will adhere to all collision scenarios. When a
collision occurs, RIC2A will switch to a jam pattern to com-
ply with IEEE repeater specifications.
FIFO Condition Overview
Elasticity buffer error (ELBER) or FIFO overflow burst is
another condition that could take place anytime during the
packet transmission. The sequence of events for FIFO
burst is the same as those for collision.
Data Repetition Process
The first task to be performed is PORT N identification.
This is an arbitration process performed by the Port State
Machines in the system. In situations where two or more
ports simultaneously receive packets, the Inter-RIC bus
operates by choosing one of the active ports, and forcing
the others to transmit data (real data or pseudo random
data). This is done in accordance with the IEEE specifica-
tion's allowed exit paths from the IDLE state, i.e., to the
SEND PREAMBLE PATTERN or RECEIVE COLLISION
states.
The packet begins with a preamble pattern derived from
the RIC2A's on chip jam/preamble generator. The data
received at PORT N is directed through the receive multi-
plexor to the PLL decoder. Once phase lock has been
achieved, the decoded data (in NRZ format) with its associ-
ated clock and enable signals, is asserted onto the IRD,
IRC, and IRE of the Inter-RIC bus. This serial data stream
is received from the bus by all RIC2As in the repeater and
directed to their elasticity buffers. Logic circuits monitor the
data stream and look for the Start of Frame Delimiter
(SFD). When it has been detected, data is loaded into the
elasticity buffer for later transmission. This will occur when
sufficient preamble has been transmitted and certain inter-
nal state machine operations have been fulfilled.
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