DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 62

• Manufacturer Part Number: DP83953VUL
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83953VUL

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 870mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83953VUL

7.0 RIC2A Registers
Event Count and Interrupt Mask Register 2 (ECIMR-2) (Page 0H Address 15H)
The bits in this register effect the Port Event Count Register 2, PECR-2 on Page 4, Addresses 11H to 1DH.
Bit
D0
D1
D2
D3
D4
D5
D6
D7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D7
res
R
PARTC-2
OWCC-2
ISAM
Symbol
ROR-2
FWF-2
FCSC
FAEC
ISAM
D6
resv
(Continued)
FWF-2
D5
Frame Check Sequence Count Enable: This bit enables counting the packets
with frame check sequence error.
0: Disable the frame check sequence count.
1: Enable the frame check sequence count.
Frame Alignment Error Count Enable: This bit enables counting the packets
with frame alignment error.
0: Disable the frame alignment error count.
1: Enable the frame alignment error count.
Partition Count Enable: This bit enables recording of partition events.
0: Disable the partition count.
1: Enable the partition count.
Out of Window Collision Count Enable: This bit enables counting of out of
window collision events.
0: Disable the out of window collision count.
1: Enable the out of window collision count.
Reset On Read: This bit enables the counter register to reset upon reading the
port event's counter.
0: No effect upon reading the register contents.
1: The counter register is reset by reading the contents of the
Freeze When Full: This bit controls the freezing of the Event Count registers
when the counter is full (FF Hex).
0: No effect on the event count register.
1: Freeze the event count register when the counter is full.
Interrupt on the Source Address Mismatch Mask
0: Interrupts will be generated on a source address mismatch
1: No interrupts are generated.
Reserved for Future Use
reads as a logic 0
mask. (RTI pin becomes active.)
register.
ROR-2
D4
62
OWCC-2
D3
Description
PARTC-2
D2
FAEC
D1
FCSC
D0
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