DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 59

• Manufacturer Part Number: DP83953VUL
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83953VUL

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 870mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83953VUL

7.0 RIC2A Registers
Real Time Interrupt Register (Address 0FH)
The Real Time Interrupt register (RTI) contains information which may change on a packet by packet basis. Any remain-
ing interrupts which have not been serviced before the following packet is transmitted are cleared. Since multiple interrupt
sources may be displayed by the RTI a priority scheme is implemented. A read cycle to the RTI gives the interrupt source
and an address vector indicating the RIC2A port that generated the interrupt.
The order of priority for the display of interrupt information is as follows (in secure mode only):
1. Source Address Mismatch (feature of the RIC2A that is not present in the RIC.)
2. The receive source of network activity (Port N),
3. The first RIC2A port showing collision,
4. A port partitioned or reconnected.
During the repetition of a single packet it is possible that multiple ports may be partitioned or alternatively reconnected.
The ports have equal priority in displaying partition/reconnection information. This data is derived from the ports by the
RTI register as it polls consecutively around the ports.
Reading the RTI clears the particular interrupt for all cases. If no interrupt sources are active, the RTI returns a no valid
interrupt status.
The following table shows the mapping of interrupt sources onto the D3 to D0 pins. Essentially each of the three interrupt
sources has a dedicated bit in this field. If a read to the RTI produces a low logic level on one of these bits then the inter-
rupt source may be directly decoded. Associated with the source of the interrupt is the port where the event is occurring.
If no unmasked events (receive, collision, etc.) have occurred when the RTI is read, then an all ones pattern is driven by
the RIC2A onto the data pins.
D(3:0)
D(7:4)
PA3
PA3
PA3
PA3
Bit
D7
1
R
R
PA2
R/W
PA2
PA2
PA2
D6
1
IVCTR3
D7
ISCR(3:0)
IVCTR(3:0)
PA1
PA1
PA1
PA1
D5
1
Symbol
Access
IVCTR2
D6
(Continued)
PA0
PA0
PA0
PA0
D4
1
IVCTR1
Interrupt Source
These four bits indicate the reason why the interrupt was generated.
Interrupt Vector
This field defines the port address responsible for generating the interrupt.
D3
1
1
1
0
1
D5
D2
1
1
0
1
1
IVCTR0
D4
D1
1
0
1
1
1
59
ISRC3
D3
D0
0
1
1
1
1
ISRC2
Description
D2
PA(3:0) = port address for the mismatch
PA(3:0) = collision port address
PA(3:0) = partition port address
PA(3:0) = receive port address
Source Address Mismatch
ISRC1
partition reconnection
D1
no valid interrupt
first collision
Comments
receive
ISRC0
D0
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