DS21448L+ Maxim Integrated Products, DS21448L+ Datasheet - Page 18

• Manufacturer Part Number: DS21448L+
• Description: IC LIU QUAD E1/T1/J1 128-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS21448L+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Framer
• Number Of Transceivers: 4
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 400 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3 Parallel Port Operation
The option for either multiplexed bus operation (BIS0 = 0) or nonmultiplexed bus operation (BIS0 = 1) is available
when using the parallel interface. The DS21448 can operate with either Intel or Motorola bus timing configurations.
If the PBTS pin is wired low, Intel timing is selected; if wired high, Motorola timing is selected. All Motorola bus
signals are listed in parentheses (). Four sets of identical register maps exist, one for each channel. See
for register names and addresses. Use the appropriate chip select (CS1, CS2, CS3, or CS4) to access a channel’s
register map. See the timing diagrams in Section
supported when using parallel port operation.
4.3.1
The DS21448 resets itself upon power-up, setting all writeable registers to 00h and clearing the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the power
supplies have settled, initialize all control registers to the desired settings, then toggle the LIRST bit (CCR3.2). The
DS21448 can at any time be reset to the default settings by bringing HRST low (level triggered) or by powering
down and powering up again.
Table 4-G. Parallel Port Mode Selection
4.3.2
Table 4-H
to access a channel’s register map.
Table 4-H. Register Map
Note 1: Register addresses 16h–1Fh do not exist.
RUPCD1
RUPCD2
RDNCD1
RDNCD2
TEST1
TEST2
TEST2
PBTS
NAME
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
TCD1
TCD2
ECR1
ECR2
IBCC
RIR1
RIR2
IMR
SR
—
0
0
1
1
Device Power-Up and Reset
Register Map
shows the typical register map for all four ports. Use the appropriate chip select (CS1, CS2, CS3, or CS4)
BIS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
0
1
0
1
R
R
R
R
R
PROCESSOR
ADDRESS
(Note 1)
Motorola
Motorola
0Ah
0Bh
0Ch
0Dh
0Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
10h
11h
12h
13h
14h
15h
Intel
Intel
Common Control Register 1
Common Control Register 2
Common Control Register 3
Common Control Register 4
Common Control Register 5
Common Control Register 6
Status Register
Interrupt Mask Register
Receive Information Register 1
Receive Information Register 2
In-Band Code Control Register
Transmit Code Definition Register 1
Transmit Code Definition Register 2
Receive-Up Code Definition Register 1
Receive-Up Code Definition Register 2
Receive-Down Code Definition Register 1
Receive-Down Code Definition Register 2
Error Count Register 1
Error Count Register 2
Test 1
Test 2
Test 3
—
Parallel Port Mode (Nonmultiplexed)
Parallel Port Mode (Nonmultiplexed)
Parallel Port Mode (Multiplexed)
Parallel Port Mode (Multiplexed)
BUS INTERFACE TYPE
FUNCTION
10
18 of 60
for more details. Hardware and serial port modes are not
Table 4-H