DS21448L+ Maxim Integrated Products, DS21448L+ Datasheet - Page 28

• Manufacturer Part Number: DS21448L+
• Description: IC LIU QUAD E1/T1/J1 128-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS21448L+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Framer
• Number Of Transceivers: 4
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 400 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. DIAGNOSTICS
6.1 In-Band Loop-Code Generation and Detection
The DS21448 can generate and detect a repeating bit pattern from 1 to 8 or 16 bits in length. To transmit a pattern,
the user loads the pattern into the transmit code definition (TCD1 and TCD2) registers and selects the proper
length of the pattern by setting the TC0 and TC1 bits in the in-band code control (IBCC) register. When generating
a 1-, 2-, 4-, 8-, or 16-bit pattern, the transmit code registers (TCD1 and TCD2) must be filled with the proper code.
Generation of a 1-, 3-, 5-, or 7-bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern is
transmitted, as long as the TLCE control bit (CCR3.3) is enabled. For example, if the user wished to transmit the
standard loop-up code for CSUs, which is a repeating pattern of ...10000100001..., then 80h would be loaded into
TCD1, and the length would set using TC1 and TC0 in the IBCC register to 5 bits.
The DS21448 can detect two separate repeating patterns to allow for a loop-up code and a loop-down code to be
detected. The user programs the codes in the receive-up code definition (RUPCD1 and RUPCD2) registers and the
receive-down code definition (RDNCD1 and RDNCD2) registers; the length of each pattern is selected through the
IBCC register. The DS21448 detects repeating pattern codes with bit-error rates as high as 1 x 10
detector has a nominal integration period of 48ms, so after approximately 48ms of receiving either code, the proper
status bit (LUP at SR.7 and LDN at SR.6) is set to 1. Normally codes are sent for a period of 5 seconds. It is
recommended that the software poll the DS21448 every 100ms to 1000ms until 5 seconds has elapsed to ensure
the code is continuously present.
IBCC (0AH): In-Band Code Control Register
(MSB)
NAME
RUP2
RUP1
RUP0
RDN2
RDN1
RDN0
TC1
TC1
TC0
POSITION
IBCC.7
IBCC.6
IBCC.5
IBCC.4
IBCC.3
IBCC.2
IBCC.1
IBCC.0
TC0
Transmit Code Length Definition Bit 1
Transmit Code Length Definition Bit 0.
Receive Up Code Length Definition Bit 2
Receive-Up Code Length Definition Bit 1
Receive-Up Code Length Definition Bit 0
Receive-Down Code Length Definition Bit 2
Receive-Down Code Length Definition Bit 1
Receive-Down Code Length Definition Bit 0
RUP2
RUP1
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
28 of 60
RUP0
(Table
(Table 6-A)
FUNCTION
(Table 6-B)
(Table
(Table
(Table
(Table
(Table
6-A)
6-B)
6-B)
6-B)
6-B)
6-B)
RDN2
RDN1
-2
. The code
RDN0
(LSB)