PIC16F819-I/SO Microchip Technology Inc., PIC16F819-I/SO Datasheet - Page 17

• Manufacturer Part Number: PIC16F819-I/SO
• Description: 18 PIN, 3.5 KB FLASH, 256 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F819-I/SO

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 2-1:
 2004 Microchip Technology Inc.
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
Legend:
Note 1:
Bank 2
Bank 3
(1)
(1
(1)
(1)
(1)
(1)
(1)
(1)
(1,2)
(1)
(1,2)
(1)
2:
3:
INDF
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
INDF
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
Name
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Latch when written; PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
EEPROM/Flash Data Register Low Byte
EEPROM/Flash Address Register Low Byte
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
EEPROM Control Register 2 (not a physical register)
Reserved; maintain clear
Reserved; maintain clear
EEPGD
RBPU
Bit 7
GIE
GIE
IRP
IRP
—
—
—
—
INTEDG
Bit 6
PEIE
PEIE
RP1
RP1
—
—
—
—
—
EEPROM/Flash Data Register High Byte
TMR0IE
TMR0IE
T0CS
Bit 5
RP0
RP0
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
Write Buffer for the upper 5 bits of the Program Counter
FREE
T0SE
INTE
INTE
Bit 4
TO
TO
—
WRERR
RBIE
RBIE
Bit 3
PSA
PD
PD
—
EEPROM/Flash Address Register
High Byte
TMR0IF
TMR0IF
WREN
Bit 2
PS2
Z
Z
PIC16F818/819
Bit 1
INTF
INTF
PS1
WR
DC
DC
RBIF
RBIF
Bit 0
PS0
RD
C
C
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx xxxx
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
--xx xxxx
---- -xxx
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
---0 0000
0000 000x
x--x x000
---- ----
0000 0000
0000 0000
POR, BOR
DS39598E-page 15
Value on
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—
—
—
—
—
—
—
Details on
17, 54
page:
23
53
23
16
23
—
43
—
—
—
23
18
25
25
25
25
23
23
16
23
—
43
—
—
—
23
18
26
25
—
—