PIC16F819-I/SO Microchip Technology Inc., PIC16F819-I/SO Datasheet - Page 69

• Manufacturer Part Number: PIC16F819-I/SO
• Description: 18 PIN, 3.5 KB FLASH, 256 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F819-I/SO

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 9-2:
TABLE 9-2:
 2004 Microchip Technology Inc.
0Bh,8Bh
10BH,18Bh
0Ch
8Ch
86h
0Eh
0Fh
10h
15h
16h
17h
Legend:
Special event trigger will:
• Reset Timer1 but not set interrupt flag bit, TMR1IF
• Set GO/DONE bit (ADCON0<2>) which starts an A/D
Address
CCP1 pin
(PIR1<0>)
conversion
Output Enable
TRISB<x>
Compare Mode
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
INTCON
PIR1
PIE1
TRISB
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
Name
Q
Special Event Trigger
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
R
S
CCP1CON<3:0>
Mode Select
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
PORTB Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Bit 7
GIE
—
—
—
—
(PIR1<2>)
Set Flag bit CCP1IF
Match
PEIE
ADIF
ADIE
Bit 6
—
—
CCPR1H CCPR1L
TMR1H
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR0IE
CCP1X
Comparator
Bit 5
—
—
TMR1L
CCP1Y
INTE
Bit 4
—
—
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SSPIE
SSPIF
RBIE
Bit 3
9.2.1
The user must configure the CCP1 pin as an output by
clearing the TRISB<x> bit.
9.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
9.2.4
In this mode, an internal hardware trigger is generated
that may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1
register to effectively be a 16-bit programmable period
register for Timer1.
Note:
Note 1: Clearing the CCP1CON register will force
TMR0IF
CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
Bit 2
2: The TRISB bit (2 or 3) is dependent upon
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP1
module will not set interrupt flag bit,
TMR1IF (PIR1<0>).
the CCP1 compare output latch to the
default low level. This is not the data
latch.
the setting of configuration bit 12
(CCPMX).
Bit 1
INTF
PIC16F818/819
RBIF
Bit 0
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOR
Value on
DS39598E-page 67
Value on
all other
Resets