PIC16F819-I/SO Microchip Technology Inc., PIC16F819-I/SO Datasheet - Page 76

• Manufacturer Part Number: PIC16F819-I/SO
• Description: 18 PIN, 3.5 KB FLASH, 256 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F819-I/SO

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F818/819
FIGURE 10-1:
TABLE 10-1:
DS39598E-page 74
0Bh,8Bh
10Bh,18Bh
0Ch
8Ch
86h
13h
14h
94h
Legend:
RB1/SDI/SDA
Address
RB2/SDO/
RB4/SCK/
RB5/SS
CCP1
SCL
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI™ mode.
INTCON
PIR1
PIE1
TRISB
SSPBUF
SSPCON
SSPSTAT
Name
Read
SS Control
REGISTERS ASSOCIATED WITH SPI™ OPERATION
TRISB<4>
Select
Edge
bit 0
SSPM3:SSPM0
Enable
SSP BLOCK DIAGRAM
(SPI™ MODE)
Select
SSPBUF reg
Edge
PORTB Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN
Bit 7
SMP
GIE
SSPSR reg
—
—
Clock Select
4
ADIF
ADIE
Bit 6
PEIE
CKE
2
Prescaler
4, 16, 64
TMR2 Output
Write
Clock
TMR0IE
Shift
Bit 5
Data Bus
D/A
—
—
Internal
2
T
CY
Bit 4
INTE
CKP
—
—
P
SSPM3 SSPM2
SSPIF
SSPIE
RBIE
Bit 3
S
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, reinitialize the SSPCON
register and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISB register)
appropriately programmed. That is:
• SDI must have TRISB<1> set
• SDO must have TRISB<2> cleared
• SCK (Master mode) must have TRISB<4> cleared
• SCK (Slave mode) must have TRISB<4> set
• SS must have TRISB<5> set
Note 1: When
TMR0IF
CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
Bit 2
R/W
2: If the SPI is used in Slave mode with
3: When
with the SS
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS pin is set to V
CKE = 1, then the SS pin control must be
enabled.
with the SS
(SSPCON<3:0> = 0100), the state of the
SS pin can affect the state read back from
the TRISB<2> bit. The peripheral OE
signal from the SSP module into PORTB
controls the state that is read back from
the TRISB<2> bit. If read-modify-write
instructions, such as BSF are performed
on the TRISB register while the SS pin is
high, this will cause the TRISB<2> bit to
be set, thus disabling the SDO output.
SSPM1
INTF
Bit 1
UA
the
the
SSPM0 0000 0000 0000 0000
RBIF
Bit 0
BF
 2004 Microchip Technology Inc.
SPI
SPI
pin
pin
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
POR, BOR
Value on
is
is
control
control
in
in
Slave
Slave
Value on
DD
all other
Resets
enabled
enabled
.
mode
mode