PIC16F819-I/SO Microchip Technology Inc., PIC16F819-I/SO Datasheet - Page 81

• Manufacturer Part Number: PIC16F819-I/SO
• Description: 18 PIN, 3.5 KB FLASH, 256 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F819-I/SO

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.3.2
Master mode operation is supported in firmware using
interrupt generation on the detection of the Start and
Stop conditions. The Stop (P) and Start (S) bits are
cleared from a Reset or when the SSP module is dis-
abled. The Stop (P) and Start (S) bits will toggle based
on the Start and Stop conditions. Control of the I
may be taken when the P bit is set or the bus is Idle and
both the S and P bits are clear.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISB<4,1> bit(s). The output level is always low,
irrespective of the value(s) in PORTB<4,1>. So when
transmitting data, a ‘1’ data bit must have the
TRISB<1> bit set (input) and a ‘0’ data bit must have
the TRISB<1> bit cleared (output). The same scenario
is true for the SCL line with the TRISB<4> bit. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Master mode operation can be done with either the
Slave mode Idle (SSPM3:SSPM0 = 1011) or with the
Slave mode active. When both Master mode operation
and Slave modes are used, the software needs to
differentiate the source(s) of the interrupt.
For more information on Master mode operation, see
AN554, “Software Implementation of I
Master” (DS00554).
TABLE 10-3:
 2004 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
8Ch
13h
93h
14h
94h
86h
Legend:
Note 1:
Address
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.
Shaded cells are not used by SSP module in SPI™ mode.
Maintain these bits clear in I
MASTER MODE OPERATION
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPSTAT
TRISB
Name
REGISTERS ASSOCIATED WITH I
Synchronous Serial Port (I
PORTB Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
SMP
WCOL
Bit 7
GIE
—
—
(1)
SSPOV
CKE
PEIE
ADIF
ADIE
Bit 6
2
(1)
C mode.
2
C module.
TMR0IE
SSPEN
Bit 5
2
D/A
—
—
C™ Bus
2
2
C™ mode) Address Register
C bus
Bit 4
INTE
CKP
—
—
P
2
SSPM3 SSPM2 SSPM1 SSPM0
C™ OPERATION
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
RBIE
Bit 3
S
10.3.3
In Multi-Master mode operation, the interrupt genera-
tion on the detection of the Start and Stop conditions
allows the determination of when the bus is free. The
Stop (P) and Start (S) bits are cleared from a Reset or
when the SSP module is disabled. The Stop (P) and
Start (S) bits will toggle based on the Start and Stop
conditions. Control of the I
bit P (SSPSTAT<4>) is set or the bus is Idle and both
the S and P bits clear. When the bus is busy, enabling
the SSP interrupt will generate the interrupt when the
Stop condition occurs.
In Multi-Master mode operation, the SDA line must be
monitored to see if the signal level is the expected
output level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISB<4,1>). There are two stages
where this arbitration can be lost:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the Slave device
continues to receive. If arbitration was lost during the
address transfer stage, communication to the device
may be in progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data
transfer stage, the device will need to retransfer the
data at a later time.
For more information on Multi-Master mode operation,
see AN578, “Use of the SSP Module in the I
Multi-Master Environment” (DS00578).
TMR0IF
Bit 2
R/W
MULTI-MASTER MODE OPERATION
Bit 1
INTF
UA
PIC16F818/819
RBIF
Bit 0
BF
2
C bus may be taken when
0000 000x 0000 000u
-0-- 0000 -0-- 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
POR, BOR
Value on
DS39598E-page 79
Value on
all other
Resets
2
C™