PIC16F819-I/SO Microchip Technology Inc., PIC16F819-I/SO Datasheet - Page 89

• Manufacturer Part Number: PIC16F819-I/SO
• Description: 18 PIN, 3.5 KB FLASH, 256 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F819-I/SO

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.5
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
TABLE 11-2:
 2003 Microchip Technology Inc.
0Bh,8Bh
10Bh,18Bh
0Ch
8Ch
1Eh
9Eh
1Fh
9Fh
05h
85h
Legend:
Address
Note:
A/D Operation During Sleep
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in Sleep, ensure the SLEEP
instruction
instruction that sets the GO/DONE bit.
INTCON
PIR1
PIE1
ADRESH
ADRESL
ADCON0 ADCS1 ADCS0
ADCON1
PORTA
TRISA
Name
REGISTERS/BITS ASSOCIATED WITH A/D
TRISA7 TRISA6 TRISA5 PORTA Data Direction Register
A/D Result Register High Byte
A/D Result Register Low Byte
ADFM
Bit 7
RA7
GIE
—
—
immediately
ADCS2
PEIE
ADIF
ADIE
Bit 6
RA6
TMR0IE INTE
CHS2
follows
Bit 5
RA5
—
—
—
CHS1 CHS0 GO/DONE
Bit 4
RA4
—
—
—
the
PCFG3
SSPIE
SSPIF
RBIE
Bit 3
RA3
11.6
A device Reset forces all registers to their Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The value that is in the ADRESH:ADRESL registers
is
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
11.7
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with
ADRESH:ADRESL to the desired location). The appro-
priate analog input channel must be selected and the
minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module but will still reset the Timer1 counter.
TMR0IF
CCP1IE
CCP1IF
PCFG2
Bit 2
RA2
not
minimal
Effects of a Reset
Use of the CCP Trigger
modified
TMR2IF TMR1IF -0-- 0000
TMR2IE TMR1IE -0-- 0000
PCFG1
INTF
Bit 1
RA1
—
PIC16F818/819
software
PCFG0
ADON
for
RBIF
Bit 0
RA0
bits
a
overhead
0000 000x
xxxx xxxx
xxxx xxxx
0000 00-0
00-- 0000
xxx0 0000
1111 1111
POR, BOR
Power-on
(CCP1CON<3:0>)
Value on
DS39598D-page 87
(moving
Reset.
0000 000u
-0-- 0000
-0-- 0000
uuuu uuuu
uuuu uuuu
0000 00-0
00-- 0000
uuu0 0000
1111 1111
Value on
all other
Resets
The
the
be