PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 322

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
FIGURE 23-13:
TABLE 23-17: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
DS39682B-page 320
Param
70
71
71A
72
72A
73A
74
75
76
77
78
79
80
82
83
Note 1:
No.
Note:
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDI
SDIx
2:
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SC
SC
SS
SC
SC
SS
SS
SC
SC
SC
SC
SS
SC
SC
Symbol
B
DO
DO
2
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
L2
L2
L2
H2
H2
L2
H2
L2
Refer to Figure 23-3 for load conditions.
H
L
H2
L2
R
F
B
R
F
DO
DO
SS
SC
SC
DI
DO
SS
DO
DI
L
H
L,
H,
L
V
V SDOx Data Output Valid after SSx ↓ Edge
H,
V,
Z SSx ↑ to SDOx Output High-Impedance
SSx ↓ to SCKx ↓ or SCKx ↑ Input
SCKx Input High Time
(Slave mode)
SCKx Input Low Time
(Slave mode)
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDIx Data Input to SCKx Edge
SDOx Data Output Rise Time
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
SDOx Data Output Valid after SCKx Edge
SSx ↑ after SCKx Edge
82
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
70
MSb In
MSb
74
71
75, 76
Characteristic
72
bit 6 - - - - - - 1
bit 6 - - - - 1
Preliminary
Continuous
Single Byte
Continuous
Single Byte
80
LSb
LSb In
1.25 T
1.25 T
1.5 T
Min
T
100
CY
40
40
CY
10
—
—
—
—
—
—
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
© 2006 Microchip Technology Inc.
77
Max Units Conditions
25
25
50
25
25
50
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)